QT60240-ATG-SL924 Atmel, QT60240-ATG-SL924 Datasheet - Page 12

• Manufacturer Part Number: QT60240-ATG-SL924
• Description: Interface - Specialized Integrated Circuit
• Manufacturer: Atmel

Specifications of QT60240-ATG-SL924

• Product Category: Interface - Specialized
• Rohs: yes
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: MLF-32
• Minimum Operating Temperature: - 40 C

4 Control Commands
4.1 Introduction
The devices feature a set of commands which are used for
control and status reporting.
As well as Table 4.1 refer to Table 6.1, page 21 for further
details.
Poll rate: The host can make use of the CHANGE pin output
to initiate a communication; this will guarant ee the optimal
polling rate.
If the host cannot make use of the CHANGE pin the poll rate
in normal ‘run’ operation should be no faster than once per
matrix scan (see Section 7.4, page 23). Typically 10 to 20ms
is more than fast enough to extract the key status. Anything
faster will not provide new information and will slow down the
chip operation.
Sending or reading the setup block is an exception, in this
case the host can send the data at the maximum possible
rate.
Run Poll Sequence: In normal run mode the host should
limit traffic with a minimalist control structure. The host should
just read the three detect status registers (see Figure 4.1,
page 14).
Repeated Start: Using repeated start is not allowed and can
cause communication failure.
4.2 Writing Data to the Device
The sequence of events required to write data to the device is
shown next.
lQ
Address
4 to 123
131 to
S
125
130
253
0
1
2
3
Key
S
SLA+W
A
MemAddress
Data
P
SLA+W
Reserved
Detect status for keys 0 to 7, one bit
per key
Detect status for keys 8 to 15, one bit
per key
Detect status for keys 16 to 23, one
bit per key
Data for keys 0 to 23, in sequence.
Refer to Table 4.3 for details
Recalibrate all keys. Write 0x55 to
this address location to recalibrate all
the keys
Setups write-unlock. Write 0x55
immediately before writing setups
Setups - refer to Table 5.2 for details
Table 4.1 Memory Map
A
Host to Device
MemAddress
Start condition
Slave address plus write bit
Acknowledge bit
Target memory address within
device
Data to be written
Stop condition
Use
A
Data
Device to Host
Read/Write
Access
Read
Read
Read
Read
Read
Write
Write
A
P
12
The host initiates the transfer by sending the START
condition, and follows this by sending the slave address of
the device together with the Write-bit. The device sends an
ACK. The host then sends the memory address within the
device it wishes to write to. The device sends an ACK. The
host transmits one or more data bytes; each will be
acknowledged by the device.
If the host sends more than one data byte, they will be written
to consecutive memory addresses. The device automatically
increments the target memory address after writing each data
byte. After writing the last data byte, the host should send the
STOP condition.
The host should not try to write beyond address 255 because
the device will not increment the internal memory address
beyond this.
4.3 Reading Data From the Device
The sequence of events required to read data from the device
is shown next.
The host initiates the transfer by sending the START
condition, and follows this by sending the slave address of
the device together with the Write-bit. The device sends an
ACK. The host then sends the memory address within the
device it wishes to read from. The device sends an ACK.
The host must then send a STOP and a START condition
followed by the slave address again but this time
accompanied by the Read-bit. The device will return an ACK,
followed by a data byte. The host must return either an ACK
or NACK. If the host returns an ACK, the device will
subsequently transmit the data byte from the next address.
Each time a data byte is transmitted, the device automatically
increments the internal address. The device will continue to
return data bytes until the host responds with a NACK. The
host should terminate the transfer by issuing the STOP
condition.
4.4 Report Detections for All Keys
Address 1: detect status for keys 0 to 7
Address 2: detect status for keys 8 to 15
Address 3: detect status for keys 16 to 23
Each location indicates all keys in detection, if any, as a
bitfield; touched keys report as 1’s, untouched or disabled
keys report as 0’s.
Note: the change pin is cleared on reading address 1.
S
SLA+W
Data 1
Key
S
SLA+W
A
MemAddress
Data
P
SLA+R
/A
A
A
Host to Device
MemAddress
Data 2
Start condition
Slave address plus write bit
Acknowledge bit
Target memory address within
device
Data from device
Stop condition
Slave address plus read bit
Not Acknowledge bit/indicates
last byte transmission
QT60240-ISG R8.06/0906
A
A
P
S
Device to Host
SLA+R
Data n
A
/A
P