IDT74ALVCH16903PAG IDT, Integrated Device Technology Inc, IDT74ALVCH16903PAG Datasheet - Page 7

• Manufacturer Part Number: IDT74ALVCH16903PAG
• Description: IC UNIV BUS DVR 12BIT 56TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 74ALVCHr

Specifications of IDT74ALVCH16903PAG

• Logic Type: Universal Bus Driver, CMOS
• Number Of Circuits: 12-Bit
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74ALVCH16903PAG

SWITCHING CHARACTERISTICS
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. T
2
IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
Symbol
t
Skew between any two outputs of the same package and switching in the same direction.
f
SK(O)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
MAX
PZH
PZH
PHZ
PHZ
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PZL
PZL
PLZ
PLZ
t
t
t
t
t
t
t
t
SU
SU
SU
SU
SU
SU
SU
t
t
t
t
t
t
t
t
W
H
H
H
H
H
H
H
H
Parameter
Propagation Delay, Buffer Mode
xAx to xYx
Propagation Delay, Both Modes
CLK to YERR
Propagation Delay, Both Modes
CLK to PARI/O
Propagation Delay, Both Modes
CLK to PARI/O
Propagation Delay, Both Modes
Mode to xYx
Propagation Delay, Register Mode
CLK to xYx
Propagation Delay, Both Modes
OE to YERR
Propagation Delay, Both Modes
OE to YERR
Output Enable Time, Both Modes
OE to xYx
Output Enable Time, Both Modes
PAROE to PARI/O
Output Disable Time, Both Modes
OE to xYx
Output Disable Time, Both Modes
PAROE to PARI/O
Set-up Time, Register Mode, 1A-12A before CLK↑
Set-up Time, Buffer Mode, 1A to 10A before CLK↑
Set-up Time, Register Mode, APAR before CLK↑
Set-up Time, Buffer Mode, APAR before CLK↑
Set-up Time, Both Modes, PARI/O before CLK↑
Set-up Time, Buffer Mode, 11A/YERREN before CLK↑
Set-up Time, Register Mode, CLKEN before CLK↑
Hold Time, Register Mode, 1A-12A after CLK↑
Hold Time, Buffer Mode, 1A-10A after CLK↑
Hold Time, Register Mode, APAR after CLK↑
Hold Time, Buffer Mode, APAR after CLK↑
Hold Time, Register Mode, PARI/O after CLK↑
Hold Time, Buffer Mode, PARI/O after CLK↑
Hold Time, Buffer Mode, 11A/YERREN after CLK↑
Hold Time, Register Mode, CLKEN after CLK↑
Pulse Width, CLK↑
Output Skew
(2)
A
= – 40°C to + 85°C.
(1)
7
V
CC
Min.
0.25
0.25
0.25
0.25
0.25
0.25
125
1.2
1.2
1.1
1.7
5.9
1.2
4.6
2.4
2.5
0.4
0.7
—
1
1
1
1
1
1
1
1
1
1
2
3
= 2.5V ± 0.2V
Max.
4.4
5.7
8.6
6.8
5.9
6.1
5.9
3.6
5.1
6.5
5.6
6.4
3.2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min.
0.25
0.25
0.25
0.25
0.25
0.25
125
1.9
5.2
1.5
3.6
1.9
2.6
0.4
0.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
3
V
CC
= 2.7V
INDUSTRIAL TEMPERATURE RANGE
Max.
4.2
4.9
7.9
5.2
5.8
5.5
4.9
4.2
4.9
6.4
5.2
3.8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
6
V
CC
Min.
1.45
0.55
0.25
0.25
125
1.1
1.4
1.7
1.3
1.3
1.2
1.2
1.9
1.5
1.4
1.7
1.2
4.4
1.3
3.1
1.7
1.6
2.2
0.7
0.4
0.5
0.4
0.4
—
1
3
= 3.3V ± 0.3V
Max.
500
3.8
4.4
6.6
4.5
4.9
4.8
4.6
4.2
5.4
4.8
3.8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
5
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps