VP386PAG IDT, VP386PAG Datasheet - Page 7

• Manufacturer Part Number: VP386PAG
• Description: LVDS Interface IC
• Manufacturer: IDT

Specifications of VP386PAG

• Product Category: LVDS Interface IC
• Rohs: yes
• Part # Aliases: IDTVP386PAG

Note: The skew margins mean the maximum timing tolerance between the clock and data channel when the receiver still
works well. This margin takes into acount the receiver input setup and hold time, and internal clock jitter (i.e., internal data
sampling window - RSPos). Thyis margin allows for LVDS transmitter pulse position, interconnect skew, inter-symbol
interference and intrinsic channel mismatch which will cause the skew between clock (RC+ and RCK-) and data (RX[n]+
and RX[n]- ; n =0, 1, 2, 3) channels.
Thermal Characteristics
8/28-BIT LVDS RECEIVER FOR VIDEO
RCK+/- to CLKOUT Delay
Receiver PLL Setup Time
Receiver Power Down Delay
Receiver Input Strobe Position for Bit0
Receiver Input Strobe Position for Bit1
Receiver Input Strobe Position for Bit2
Receiver Input Strobe Position for Bit3
Receiver Input Strobe Position for Bit4
Receiver Input Strobe Position for Bit5
Receiver Input Strobe Position for Bit6
RxIn Skew Margin
(see note and Figure 8)
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Case
IDTVP386
8/28-BIT LVDS RECEIVER FOR VIDEO
Parameter
Parameter
RSPos0
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
Symbol
RPLLS
RCCD
RPDD
Rskm
Symbol
JA
JA
JA
JA
25 C / 3.3 V, 85MHz
f = 100 MHz, T = 10 ns
f = 100 MHz, T = 10 ns
f = 65 MHz, T = 15.38 ns
Still air
1 m/s air flow
2 m/s air flow
Conditions
7
Conditions
COMMERCIAL TEMPERATURE RANGE
2T/7-0.25
3T/7-0.25
4T/7-0.25
5T/7-0.25
6T/7-0.25
T/7-0.25
Min.
-0.25
Min.
250
500
IDTVP386
Typ.
84
76
67
50
2T/7
3T/7
4T/7
5T/7
6T/7
Typ.
14.6
T/7
0
Max.
2T/7+0.25
3T/7+0.25
5T/7+0.25
6T/7+0.25
T/7+0.25
4T/7+0.4
Max.
0.25
10
1
Units
C/W
C/W
C/W
C/W
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
7129/3
s