MAX9246EUM-T Maxim Integrated, MAX9246EUM-T Datasheet - Page 14

• Manufacturer Part Number: MAX9246EUM-T
• Description: LVDS Interface IC
• Manufacturer: Maxim Integrated

21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
Figure 12. Deserializer Serial Input in DC-Balanced Mode
Table 2. Modulation Rate
Table 3. SSG Function
Note: RxOUT_ data outputs are spread because RxCLKOUT
strobes the output of the FIFO.
14
TxIN_, DCA_, AND DCB_ ARE DATA FROM THE SERIALIZER.
______________________________________________________________________________________
SSG INPUT LEVEL
CYCLE N - 1
+
-
RxCLKIN_
RxIN2_
RxIN1_
RxIN0_
DCA2
DCA1
DCA0
f
RxCLKIN_
High
Low
DCB2
DCB1
DCB0
Mid
10
16
18
20
33
34
40
6
8
(MHz)
TxIN20
TxIN13
TxIN6
TxIN19
TxIN12
TxIN5
RxCLKOUT frequency spread
±4% relative to RxCLKIN_
RxCLKOUT frequency spread
±2% relative to RxCLKIN_
No spread on RxCLKOUT
relative to RxCLKIN_
TxIN18
TxIN11
f
TxIN4
M
(kHz) = f
TxIN17
TxIN10
TxIN3
FUNCTION
CYCLE N
15.75
17.72
19.68
32.48
33.46
39.37
RxCLKIN_
5.91
7.87
9.84
TxIN16
TxIN9
TxIN2
TxIN15
TxIN8
TxIN1
/ 1016
TxIN14
TxIN7
TxIN0
DCA2
DCA1
DCA0
To select the mid level, leave the input open, or if driven,
put the driver output in high impedance. The driver high-
impedance leakage current must be less than ±10µA.
Any spread change causes a maximum delay time of
32,800 x RCIP before output data is valid. When the
spread amount is changed from ±2% to ±4% or vice-
versa, the data outputs go low for one delay time (see
Figure 13). Similarly, when the spread is changed from
no spread to ±2% or ±4%, the data outputs go low for
one delay time (see Figure 14). The data outputs contin-
ue to switch but are not valid when the spread amount is
changed from ±2% or ±4% to no spread (see Figure
15). The spread-spectrum function is also available
when the MAX9242/MAX9244/MAX9246/MAX9254 oper-
ate in non-DC-balanced mode.
When the MAX9242/MAX9244/MAX9246/MAX9254 are
connected to an active serializer, they synchronize correct-
ly. The PLL control voltage does not saturate in response to
high-frequency glitches that may occur during a hot swap.
The PWRDWN input on the MAX9242/MAX9244/MAX9246/
MAX9254 does not need to be cycled when these devices
are connected to an active serializer.
The MAX9242/MAX9244/MAX9246/MAX9254 use two
PLLs. The first PLL (PLL1) generates a 7x clock (non-DC-
balanced mode) or a 9x clock (DC-balanced mode) from
RxCLKIN_ for deserializing the LVDS inputs. The second
PLL (SSPLL) is used for spread-spectrum modulation.
During initial power-up, the PLL1 locks, and SSPLL locks
immediately after. The PLL lock times are set by an inter-
nal counter. The maximum time to lock for each PLL is
32,800 clock periods. Power and clock should be stable
to meet the lock time specification. After initialization, if
the first PLL loses lock, it locks again and then the
DCB2
DCB1
DCB0
TxIN20
TxIN13
TxIN6
TxIN19
TxIN12
TxIN5
TxIN18
TxIN11
TxIN4
CYCLE N + 1
TxIN17
TxIN10
TxIN3
TxIN16
TxIN9
TxIN2
PLL Lock Time
TxIN15
TxIN8
TxIN1
Hot Swap
TxIN14
TxIN7
TxIN0