74VCXR162601MTD Fairchild Semiconductor, 74VCXR162601MTD Datasheet

74VCXR162601MTD

Manufacturer Part Number

74VCXR162601MTD

Description

TXRX 18BIT UNIV BUS LV 56TSSOP

Manufacturer

Fairchild Semiconductor

Series

74VCXr

Datasheet

1.74VCXR162601MTD.pdf (9 pages)

Specifications of 74VCXR162601MTD

Logic Type

Universal Bus Transceiver

Number Of Circuits

18-Bit

Current - Output High, Low

12mA, 12mA

Voltage - Supply

1.4 V ~ 3.6 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

56-TSSOP

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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74VCXR162601MTD

74VCXR162601

Low Voltage 18-Bit Universal Bus Transceivers

with 3.6V Tolerant Inputs and

Outputs and 26 Series Resistors in the Outputs

General Description

The VCXR162601, 18-bit universal bus transceiver, com-

bines D-type latches and D-type flip-flops to allow data flow

in transparent, latched, and clocked modes.

Data flow in each direction is controlled by output-enable

(OEAB and OEBA), latch-enable (LEAB and LEBA), and

clock (CLKAB and CLKBA) inputs. The clock can be con-

trolled by the clock-enable (CLKENAB and CLKENBA)

inputs. For A-to-B data flow, the device operates in the

transparent mode when LEAB is HIGH. When LEAB is

LOW, the A data is latched if CLKAB is held at a HIGH-to-

LOW logic level. If LEAB is LOW, the A bus data is stored

in the latch/flip-flop on the LOW-to-HIGH transition of

CLKAB. Output-enable OEAB is active-LOW. When OEAB

is HIGH, the outputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B but uses

OEBA, LEBA, CLKBA and CLKENBA.

The 74VCXR162601 is designed for low voltage (1.4V to

3.6V) V

The VCXR162601 is also designed with 26

tors on both the A and B Port outputs. This design reduces

line noise in applications such as memory address drivers,

clock drivers, and bus transceivers/transmitters.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Order Number

applications with I/O compatibility up to 3.6V.

Package

Number

MTD56

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

series resis-

DS500171

Features

Note 1: To ensure the high-impedance state during power up or power

down, OE should be tied to V

value of the resistor is determined by the current-sourcing capability of the

driver.

1.4V to 3.6V V

3.6V tolerant inputs and outputs

26 series resistors on both the A and B Port outputs.

Power-down HIGH impedance inputs and outputs

Supports live insertion/withdrawal (Note 1)

Static Drive (I

Uses patented noise/EMI reduction circuitry

Latchup performance exceeds 300 mA

ESD performance:

3.8 ns max for 3.0V to 3.6V V

Human body model

Machine model 200V

12 mA @ 3.0V V

(A to B, B to A)

Package Description

supply operation

)

2000V

through a pull-up resistor; the minimum

August 1998

Revised October 2004

www.fairchildsemi.com

Related parts for 74VCXR162601MTD

74VCXR162601MTD Summary of contents

Page 1

... Ordering Code: Package Order Number Number 74VCXR162601MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2004 Fairchild Semiconductor Corporation Features 1 ...

Page 2

Connection Diagram Logic Diagram www.fairchildsemi.com Pin Descriptions Pin Names Description OEAB, OEBA Output Enable Inputs (Active LOW) LEAB, LEBA Latch Enable Inputs CLKAB, CLKBA Clock Inputs CLKENAB, CLKENBA Clock Enable Inputs A –A Side A Inputs or 3-STATE Outputs 1 ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( Outputs 3-STATED Outputs Active (Note 6) 0 Input Diode Current ( Output ...

Page 4

DC Electrical Characteristics Symbol Parameter V LOW Level Output Voltage OL I Input Leakage Current I I 3-STATE Output Leakage OZ I Power-OFF Leakage Current OFF I Quiescent Supply Current CC I Increase in I per Input CC CC Note ...

Page 5

AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency C MAX C t Propagation Delay C PHL PLH C t Propagation Delay C PHL t Clock PLH C ...

Page 6

Dynamic Switching Characteristics Symbol Parameter V Quiet Output Dynamic OLP Peak Quiet Output Dynamic OLV Valley Quiet Output Dynamic OHV Valley V OH Capacitance Symbol Parameter C Input Capacitance IN C Output Capacitance I/O ...

Page 7

AC Loading and Waveforms (V TEST PLH PHL PZL PLZ PZH PHZ FIGURE 2. Waveform for Inverting and Non-inverting Functions FIGURE 4. 3-STATE Output High Enable and Disable Times for Low ...

Page 8

AC Loading and Waveforms (V TEST PLH PHL PZL PLZ PZH PHZ FIGURE 8. Waveform for Inverting and Non-inverting Functions FIGURE 9. 3-STATE Output High Enable and Disable Times for Low ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...

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