7028L20PF IDT, 7028L20PF Datasheet
7028L20PF
Specifications of 7028L20PF
Related parts for 7028L20PF
7028L20PF Summary of contents
Page 1
... Low-power operation – IDT7028L Active: 1W (typ.) Standby: 1mW (typ.) Dual chip enables allow for depth expansion without external logic IDT7028 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device Functional Block Diagram W R/ ...
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... IDT7028L High-Speed 64K x 16 Dual-Port Static RAM Description The IDT7028 is a high-speed 64K x 16 Dual-Port Static RAM. The IDT7028 is designed to be used as a stand-alone 1024K-bit Dual-Port RAM combination MASTER/SLAVE Dual-Port RAM for 32-bit-or- more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit or wider memory system applications results in full- speed, error-free operation without the need for additional discrete logic ...
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... Military Unit Symbol -0 GND -65 to +135 -65 to +150 C NOTES > -1.5V for pulse width less than 10ns must not exceed Vcc + 10%. TERM 4836 tbl 02 Capacitance (T = +25° 1.0MHz) A > Vcc + 10%. Symbol TERM OUT NOTES: ...
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... IDT7028L High-Speed 64K x 16 Dual-Port Static RAM Truth Table I: Chip Enable < 0.2V >V -0. >V -0. <0.2V NOTES: 1. Chip Enable references are shown above with the actual and ' CMOS standby requires ' either < 0.2V or > V ...
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... IDT7028L High-Speed 64K x 16 Dual-Port Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter ( Input Leakage Current LI |I Output Leakage Current | LO V Output Low Voltage OL V Output High Voltage OH NOTES Vcc < 2.0V, input leakages are undefined. ...
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... IDT7028L High-Speed 64K x 16 Dual-Port Static RAM AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load Waveform of Read Cycles ADDR ( UB, LB R/W DATA OUT BUSY OUT Timing of Power-Up Power-Down ( NOTES: 1 ...
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... Symbol WRITE CYCLE t Write Cycle Time WC (3) t Chip Enable to End-of-Write EW t Address Valid to End-of-Write AW (3) t Address Set-up Time AS t Write Pulse Width WP t Write Recovery Time WR t Data Valid to End-of-Write DW (1,2) t Output High-Z Time HZ (4) t Data Hold Time DH t ...
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... This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2 during R/W controlled write cycle, the write pulse width must be the larger placed on the bus for the required t ...
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... IDT7028L High-Speed 64K x 16 Dual-Port Static RAM Timing Waveform of Semaphore Read after Write Timing, Either Side VALID ADDRESS SEM DATA R/W OE NOTES and for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table). ...
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... IDT7028L High-Speed 64K x 16 Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol BUSY TIMING (M/S BUSY Access Time from Address Match t BAA BUSY Disable Time from Address Not Matched t BDA BUSY Access Time from Chip Enable Low ...
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... IDT7028L High-Speed 64K x 16 Dual-Port Static RAM Timing Waveform of Write with Port-to-Port Read and BUSY (M ADDR "A" R/W "A" DATA IN "A" (1) t APS ADDR "B" BUSY "B" DATA OUT "B" NOTES ensure that the earlier of the two ports wins ...
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... IDT7028L High-Speed 64K x 16 Dual-Port Static RAM Waveform of BUSY Arbitration Controlled by CE Timing (M ADDR "A" and "B" CE "A" (2) t APS CE "B" BUSY "B" Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing (M (1) IH ADDR "A" ADDR " ...
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... IDT7028L High-Speed 64K x 16 Dual-Port Static RAM Waveform of Interrupt Timing ADDR "A" "A" R/W "A" INT "B" ADDR "B" CE "B" OE "B" INT "B" NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. ...
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... NOTES: 1. Pins BUSY and BUSY are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT7028 are L R push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes. 2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address is not met, either BUSY and enable inputs of this port ...
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... BUSY pin is an input if the part used as a slave (M/S pin = V in Figure 3. If two or more master parts were used when expanding in width, a split decision could result with one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array. ...
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... The eight semaphore flags reside within the IDT7028 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a LOW input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, CE, and R/W) as they would be used in accessing a standard Static RAM ...
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... Page 17 Added Industrial temp offering to 20ns ordering information Pages 1 & 17 Replaced 01/29/09: Page 17 Removed "IDT" from orderable part number CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 The IDT logo is a registered trademark of Integrated Device Technology, Inc Package Process/ Temperature Range parameter logo with ® ...