MAX2104CCM+TD Maxim Integrated, MAX2104CCM+TD Datasheet - Page 7

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MAX2104CCM+TD

Manufacturer Part Number
MAX2104CCM+TD
Description
Tuners
Manufacturer
Maxim Integrated
Datasheet
Figure 1. Timing Diagram
PIN
34
35
36
37
38
42
43
44
47
48
PSOUT+
PSOUT-
MOD+,
MOD-
PSOUT+
PSOUT-
PLLIN+
TANK+
PLLIN-
NAME
TANK-
MOD-
VRLO
CP
FB
EP
_______________________________________________________________________________________
50%
PECL Modulus Control. A PECL low on MOD- sets the dual-modulus prescaler to divide by 32. A PECL
logic high sets the divide ratio to 33. Drive with a differential PECL signal with MOD+ (pin 33).
PECL Phase-Locked Loop Input. Drive with a differential PECL signal with PLLIN- (pin 36).
PECL Phase-Locked Loop Input. Drive with a differential PECL signal with PLLIN+ (pin 35).
PECL Prescaler Output. Differential output of the dual-modulus prescaler. Used with PSOUT- (pin 38).
Requires PECL-compatible termination.
PECL Prescaler Output. Differential output of the dual-modulus prescaler. Used with PSOUT+ (pin 37).
Requires PECL-compatible termination.
LO Tank Oscillator Input. Connect to an external LC tank with varactor tuning.
LO Internal Regulator. Bypass with a 100pF ceramic chip capacitor to GND.
LO Tank Oscillator Input. Connect to an external LC tank with varactor tuning.
Feedback Output. Control of external charge-pump transistor.
Voltage Drive Output. Control of external charge-pump transistor.
Exposed Paddle. Connect EP to GND.
t
SUM
t
50%
50%
HM
50%
Direct-Conversion Tuner IC for
Digital DBS Applications
FUNCTION
Pin Description (continued)
7

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