IS62WV51216BLL-55TLI ISSI, Integrated Silicon Solution Inc, IS62WV51216BLL-55TLI Datasheet - Page 10

• Manufacturer Part Number: IS62WV51216BLL-55TLI
• Description: IC SRAM 8MBIT 55NS 44TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: Asynchronousr

Specifications of IS62WV51216BLL-55TLI

• Memory Size: 8M (512K x 16)
• Package / Case: 44-TSOP II
• Interface: Parallel
• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Speed: 55ns
• Voltage - Supply: 2.5 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 55 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 5 mA
• Organization: 512 K x 16
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 2.5 V to 3.6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 706-1048

IS62WV51216ALL,
WRITE CYCLE SWITCHING CHARACTERISTICS
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to
2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
4. t
AC WAVEFORMS
WRITE CYCLE NO. 1
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS1 , CS2 and WE inputs and at
2. WRITE = (CS1) [ (LB) = (UB) ] (WE).
10
Symbol
t
t
t
t
t
t
t
t
t
t
t
V
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the
write.
least one of the LB and UB inputs being in the LOW state.
WC
SCS1/
AW
HA
SA
PWB
SD
HD
HZWE
LZWE
PWE
PWE
DD
-0.2V/0.4V to V
(4)
> t
(3)
t
(3)
SCS2
HZWE
Parameter
Write Cycle Time
CS1/CS2 to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
LB, UB Valid to End of Write
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
+ t
ADDRESS
SD
LB, UB
when OE is LOW.
DOUT
DD
CS1
CS2
DIN
WE
-0.3V and output loading specified in Figure 1.
(1,2)
(CS1 Controlled, OE = HIGH or LOW)
IS62WV51216BLL
t
DATA UNDEFINED
SA
Integrated Silicon Solution, Inc. — www.issi.com —
Min.
t
AW
45
35
35
35
35
20
—
0
0
0
5
t
HZWE
45ns
t
t
SCS2
SCS1
Max.
t
t
t
PWB
—
—
—
—
—
—
—
—
—
20
—
WC
PWE
(1,2)
HIGH-Z
(Over Operating Range)
t
SD
Min.
DATA-IN VALID
55
45
45
45
40
25
—
0
0
0
5
55 ns
Max.
—
20
—
—
—
—
—
—
—
—
—
t
HA
t
t
LZWE
HD
Min.
60
70
60
60
30
50
—
0
0
0
5
70 ns
Max.
30
—
—
—
—
—
—
—
—
—
—
1-800-379-4774
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12/13/2007
Rev. D