CY7C1471BV33-117AXC Cypress Semiconductor Corp, CY7C1471BV33-117AXC Datasheet

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... SRAMs designed specifically to support unlimited true back-to-back read or write operations without the insertion of wait states. The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33 are equipped with the advanced No Bus Latency (NoBL) logic. NoBL™ is required to enable consecutive read or write operations with data being transferred on every clock cycle ...

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... Logic Block Diagram – CY7C1471BV33 (2M x 36) ADDRESS A0, A1, A REGISTER MODE CE CLK C CEN WRITE ADDRESS ADV/ READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL Logic Block Diagram – CY7C1473BV33 (4M x 18) ADDRESS A0, A1, A REGISTER MODE CE CLK WRITE ADDRESS ADV/ READ LOGIC CE1 CE2 CE3 ...

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... CLK C CEN WRITE ADDRESS REGISTER 1 ADV/ AND DATA COHERENCY READ LOGIC CE1 CE2 CE3 ZZ Sleep Control Document Number: 001-15029 Rev. *D CY7C1473BV33, CY7C1475BV33 A1 A1 A0' BURST D0 Q0 LOGIC ADV/LD C WRITE ADDRESS REGISTER 2 MEMORY WRITE ARRAY DRIVERS WRITE REGISTRY CONTROL LOGIC INPUT REGISTER 1 CY7C1471BV33 ...

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... Pin Configuration DQP DDQ BYTE DDQ DDQ BYTE DDQ DQP 30 D Document Number: 001-15029 Rev. *D CY7C1473BV33, CY7C1475BV33 Figure 1. 100-Pin TQFP Pinout CY7C1471BV33 CY7C1471BV33 80 DQP DDQ BYTE DDQ DDQ BYTE DDQ DQP A Page [+] Feedback ...

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... Pin Configuration (continued DDQ DDQ BYTE DDQ DQP DDQ Document Number: 001-15029 Rev. *D CY7C1473BV33, CY7C1475BV33 Figure 2. 100-Pin TQFP Pinout CY7C1473BV33 CY7C1471BV33 DDQ DQP DDQ BYTE DDQ DDQ Page [+] Feedback ...

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... D D DDQ DDQ DDQ N DQP DDQ P NC/144M MODE NC/576M NC/1G A CE2 DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ N DQP DDQ P NC/144M MODE A A Document Number: 001-15029 Rev. *D CY7C1473BV33, CY7C1475BV33 CY7C1471BV33 ( CEN CLK TDI A1 TDO TCK TMS CY7C1473BV33 ( ...

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... DD DDQ V CEN DDQ DDQ DDQ MODE TDI CY7C1471BV33 DQb DQb 3 BWS BWS DQb DQb b f BWS BWS DQb DQb DQb DQb DQPf DQPb DDQ DDQ V DQf V DQf DQf DQf DDQ DDQ V V DQf SS SS DQf V V DDQ DQf DQf DDQ DQa ...

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... CE to select or deselect the device and CE to select or deselect the device and CE to select or deselect the device and DQP are placed in a tri-state condition.The outputs are automatically controlled by BW correspondingly left floating selects interleaved burst sequence. DD CY7C1471BV33 . During s Page [+] Feedback ...

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... No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address expansion pins and are not internally connected to the die. Functional Overview The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33 are synchronous flow through burst SRAMs designed specifically to eliminate wait states during write-read transitions. ...

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... X the data portion of a write cycle, regardless of the state of OE. Burst Write Accesses The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33 have an on-chip burst counter that enables the user to supply a single address and conduct up to four write operations without reasserting the address inputs. ADV/LD must be driven LOW to ...

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... The truth table for CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33 follows. Truth Table Address Operation Used Deselect Cycle None Deselect Cycle None Deselect Cycle None Continue Deselect Cycle None Read Cycle External (Begin Burst) Read Cycle Next (Continue Burst) NOP/Dummy Read External (Begin Burst) ...

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... The read/write truth table for CY7C1471BV33 follows. Truth Table for Read/Write Function Read Write No bytes written Write Byte A – (DQ and DQP ) A A Write Byte B – (DQ and DQP ) B B Write Byte C – (DQ and DQP ) C C Write Byte D – (DQ and DQP ) D D Write All Bytes The read/write truth table for CY7C1473BV33 follows ...

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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33 incorporate a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM ...

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... TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. CY7C1471BV33 Page [+] Feedback ...

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... TAP Controller State Diagram TEST-LOGIC 1 RESET 0 1 RUN-TEST/ 0 IDLE Document Number: 001-15029 Rev. *D CY7C1473BV33, CY7C1475BV33 1 SELECT DR-SCA CAPTURE-DR CAPTURE-IR 0 SHIFT- EXIT1-DR 0 PAUSE- EXIT2-DR 1 UPDATE-DR UPDATE- CY7C1471BV33 1 SELECT IR-SCAN 0 0 SHIFT- EXIT1-IR 0 PAUSE- EXIT2- Page [+] Feedback ...

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... TAP Controller Block Diagram Selection TDI Circuitry TCK TM S Document Number: 001-15029 Rev. *D CY7C1473BV33, CY7C1475BV33 0 Bypass Register Selection Instruction Register Circuitry Identification Register Boundary Scan Register TAP CONTROLLER CY7C1471BV33 TDO Page [+] Feedback ...

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... OL DDQ 2.5V OL DDQ I = 100 µ 3.3V OL DDQ V = 2.5V DDQ V = 3.3V DDQ V = 2.5V DDQ V = 3.3V DDQ V = 2.5V DDQ GND < V < DDQ CY7C1471BV33 to 2.5V SS 1.25V 50Ω 50Ω 20pF O Min Max Unit 2.4 V 2.0 V 2.9 V 2.1 V 0.4 V 0.4 V 0.2 V 0 ...

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... CS CH 11.Test conditions are specified using the load in TAP AC Test Conditions. t Document Number: 001-15029 Rev. *D CY7C1473BV33, CY7C1475BV33 Description Figure 3. TAP Timing TDIS t TDIH DON’ UNDEFINED / ns CY7C1471BV33 Min Max Unit MHz ...

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... Do Not Use: This instruction is reserved for future use. 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. CY7C1471BV33 Description Describes the version number Reserved for internal use Defines memory type and architecture Defines width and density ...

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... M10 58 A8 L10 59 B8 K11 60 A7 165-Ball ID Bit # 165-Ball L10 P6 28 K10 R6 29 J10 R8 30 H11 P3 31 G11 P4 32 F11 P8 33 E11 P9 34 D11 P10 35 C11 R9 36 A11 R10 37 A9 R11 38 B9 M10 39 A10 CY7C1471BV33 Bit # 165-Ball Bit # 165-Ball ID 40 B10 ...

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... W6 71 J11 V5 72 J10 U5 73 H11 U6 74 H10 W7 75 G11 V7 76 G10 U7 77 F11 V8 78 F10 V9 79 E10 W11 80 E11 W10 81 D11 V11 82 D10 V10 83 C11 U11 84 C10 CY7C1471BV33 Bit # 209-Ball ID 85 B11 86 B10 87 A11 88 A10 100 B3 101 C3 102 C4 103 C8 104 ...

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... 0. inputs static /2). Undershoot: V (AC) > –2V (pulse width less than t CYC IL (min.) within 200 ms. During this time V < V and CY7C1471BV33 + 0.5V DD Ambient DDQ Temperature 0°C to +70°C 3.3V–5%/+10% 2.5V – –40°C to +85°C Min Max 3.135 3.6 3 ...

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... Figure 4. AC Test Loads and Waveforms R = 317 3.3V V OUTPUT DDQ GND 351 INCLUDING JIG AND (b) SCOPE R = 1667 2.5V V DDQ OUTPUT GND 1538 INCLUDING JIG AND (b) SCOPE CY7C1471BV33 165 FBGA 209 BGA Package Package 165 FBGA 209 FBGA Max Max 16.3 15 ...

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... V AC Test Loads and Waveforms is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same data OELZ CHZ CLZ CY7C1471BV33 = 3.3V and is DDQ on page 23 unless otherwise noted. 133 MHz 117 MHz Min Max Min ...

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... CDV t DOH t OEV t CLZ D(A2+1) Q(A3) Q(A4) t OEHZ t OELZ READ READ BURST Q(A3) Q(A4) READ Q(A4+1) DON’T CARE UNDEFINED is LOW. When CE is HIGH HIGH CY7C1471BV33 CHZ Q(A4+1) D(A5) Q(A6) D(A7) t DOH W RITE READ W RITE DESELECT D(A5) Q(A6) D(A7) is LOW HIGH. ...

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... The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle. Document Number: 001-15029 Rev. *D CY7C1473BV33, CY7C1475BV33 [20, 21, 23 Q(A2) Q(A3) STALL READ WRITE STALL Q(A3) D(A4) DON’T CARE UNDEFINED CY7C1471BV33 CHZ D(A4) Q(A5) t DOH NOP READ DESELECT CONTINUE Q(A5) DESELECT Page [+] Feedback ...

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... Document Number: 001-15029 Rev. *D CY7C1473BV33, CY7C1475BV33 [24, 25] Figure 7. ZZ Mode Timing High-Z DON’T CARE The truth table for CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33 follows. CY7C1471BV33 t ZZREC t RZZI DESELECT or READ Only [ Page [+] Feedback ...

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... To find the office closest to you, visit http://www.cypress.com/go/datasheet/offices. Speed Package Ordering Code (MHz) Diagram 133 CY7C1471BV33-133AXC 51-85050 100-pin Thin Quad Flat Pack ( 1.4 mm) Pb-Free CY7C1473BV33-133AXC Document Number: 001-15029 Rev. *D CY7C1473BV33, CY7C1475BV33 http://www.cypress.com/products or contact your local sales Part and Package Type CY7C1471BV33 Operating Range Commercial Page [+] Feedback ...

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... Package Diagrams Figure 8. 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) Document Number: 001-15029 Rev. *D CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 51-85050 *C Page [+] Feedback ...

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... Package Diagrams (continued) Figure 9. 165-Ball FBGA ( 1.4 mm) Document Number: 001-15029 Rev. *D CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 51-85165 *B Page [+] Feedback ...

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... Package Diagrams (continued) Figure 10. 209-Ball FBGA ( 1.76 mm) Document Number: 001-15029 Rev. *D CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 51-85167 *A Page [+] Feedback ...

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... Corrected typo in the “NOP, STALL and DESELECT Cycles” waveform Converted from preliminary to final Added footnote 16 related to IDD NJY Removed inactive parts from Ordering Information table; Updated package diagrams. VKN Removed inactive part CY7C1471BV33-117AXC from the ordering information table. Revised April 6, 2010 CY7C1471BV33 Page [+] Feedback ...