CY7C1470V25-167AXC Cypress Semiconductor Corp, CY7C1470V25-167AXC Datasheet - Page 14

• Manufacturer Part Number: CY7C1470V25-167AXC
• Description: IC SRAM 72MBIT 167MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1470V25-167AXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 72M (2M x 36)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Density: 72Mb
• Access Time (max): 3.4ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 167MHz
• Operating Supply Voltage (typ): 2.5V
• Address Bus: 21b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 4
• Supply Current: 400mA
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 2M
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

possible to capture all other signals and simply ignore the value
of the CLK captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO balls.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction will have the same
effect as the Pause-DR command.
TAP Timing
TAP AC Switching Characteristics
Over the Operating Range
Document Number: 38-05290 Rev. *L
Clock
t
t
t
t
Output Times
t
t
Set-up Times
t
t
t
Hold Times
t
t
t
Notes
Parameter
TCYC
TF
TH
TL
TDOV
TDOX
TMSS
TDIS
CS
TMSH
TDIH
CH
9. t
10. Test conditions are specified using the load in TAP AC Test Conditions. t
CS
and t
CH
refer to the set-up and hold time requirements of latching data from the boundary scan register.
TCK clock cycle time
TCK clock frequency
TCK clock HIGH time
TCK clock LOW time
TCK clock LOW to TDO valid
TCK clock LOW to TDO invalid
TMS set-up to TCK clock rise
TDI set-up to TCK clock rise
Capture set-up to TCK rise
TMS hold after TCK clock rise
TDI hold after clock rise
Capture hold after clock rise
Test Mode Select
Test Data-Out
Test Data-In
Test Clock
(TDO)
(TMS)
(TCK)
[9, 10]
(TDI)
1
Description
t TMSS
t TDIS
2
t TMSH
t TDIH
t TH
DON’T CARE
R
/t
t
TL
F
= 1 ns.
3
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
t CYC
UNDEFINED
4
t TDOX
t TDOV
5
Min
50
20
20
–
–
0
5
5
5
5
5
5
6
Max
20
10
–
–
–
–
–
–
–
–
–
–
CY7C1470V25
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CY7C1474V25
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Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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