23K640-I/SN Microchip Technology, 23K640-I/SN Datasheet - Page 10

• Manufacturer Part Number: 23K640-I/SN
• Description: IC SRAM 64KBIT 20MHZ 8SOIC
• Manufacturer: Microchip Technology
• Type: Synchronousr

Specifications of 23K640-I/SN

• Memory Size: 64K (8K x 8)
• Format - Memory: RAM
• Memory Type: SRAM
• Speed: 20MHz
• Interface: SPI Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Memory Configuration: 8K X 8
• Clock Frequency: 20MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Access Time: 25 ns
• Maximum Clock Frequency: 20 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 10 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

23A640/23K640
2.5
The Read Status Register instruction (RDSR) provides
access to the STATUS register. The STATUS register
may be read at any time. The STATUS register is
formatted as follows:
TABLE 2-2:
FIGURE 2-7:
DS22126B-page 10
W/R = writable/readable.
MODE MODE
SCK
W/R
CS
SO
7
SI
Read Status Register Instruction
(RDSR)
W/R
6
0
0
READ STATUS REGISTER TIMING SEQUENCE (RDSR)
STATUS REGISTER
5
–
0
0
1
High-Impedance
4
–
0
0
Instruction
2
3
–
0
0
3
2
–
0
0
4
1
–
1
1
HOLD
5
W/R
0
Preliminary
0
6
1
7
The mode bits indicate the operating mode of the
SRAM. The possible modes of operation are:
0 0 = Byte mode (default operation)
1 0 = Page mode
0 1 = Sequential mode
1 1 = Reserved
Write and read commands are shown in Figure 2-7 and
Figure 2-8.
The HOLD bit enables the Hold pin functionality. It must
be set to a ‘0’ before HOLD pin is brought low for HOLD
function to work properly. Setting HOLD to ‘1’ disables
feature.
Bits 2 through 5 are reserved and should always be set
to ‘0’. Bit 1 will read back as ‘1’ but should always be
written as ‘0’.
See Figure 2-7 for the RDSR timing sequence.
7
8
6
9
Data from STATUS Register
10
5
11
4
© 2009 Microchip Technology Inc.
12
3
13
2
14
1
15
0