CY62148DV30LL-55SXI Cypress Semiconductor Corp, CY62148DV30LL-55SXI Datasheet

IC SRAM 4MBIT 55NS 32SOIC

CY62148DV30LL-55SXI

Manufacturer Part Number
CY62148DV30LL-55SXI
Description
IC SRAM 4MBIT 55NS 32SOIC
Manufacturer
Cypress Semiconductor Corp
Type
Asynchronousr

Specifications of CY62148DV30LL-55SXI

Memory Size
4M (512K x 8)
Package / Case
32-SOIC (11.30mm Width)
Format - Memory
RAM
Memory Type
SRAM
Speed
55ns
Interface
Parallel
Voltage - Supply
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Access Time
55 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.2 V
Maximum Operating Current
10 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Ports
1
Operating Supply Voltage
2.5 V, 3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
428-2074-5
CY62148DV30LL-55SXI
Features
Cypress Semiconductor Corporation
Document Number : 38-05341 Rev. *F
Temperature Ranges
Very high speed: 55 ns
Pin-compatible with CY62148CV25, CY62148CV30 and
CY62148CV33
Ultra low active power
Ultra low standby power
Easy memory expansion with CE, and OE features
Automatic power-down when deselected
Complementary metal oxide semiconductor (CMOS) for
optimum speed/power
Available in Pb-free 32-pin Small-outline integrated circuit
(SOIC package)
Logic Block Diagram
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” on
Industrial: –40 °C to 85 °C
Wide voltage range: 2.20 V – 3.60 V
Typical active current: 1.5 mA at f = 1 MHz
Typical active current: 8 mA at f = f
CE
WE
OE
A
A
A
A
A
A
A
A
A
A
A
A
A
11
12
0
1
2
3
4
5
6
7
8
9
10
max
(55-ns speed)
198 Champion Court
Data in Drivers
512K x 8
ARRAY
DECODER
COLUMN
4-Mbit (512K x 8) MoBL
POWER
DOWN
Functional Description
The CY62148DV30 is a high-performance CMOS static RAM
organized as 512K words by 8 bits. This device features
advanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life™ (MoBL
applications such as cellular telephones. The device also has an
automatic power-down feature that significantly reduces power
consumption. The device can be put into standby mode reducing
power consumption when deselected (CE HIGH).The eight input
and output pins (I/O
high-impedance state when:
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the eight I/O pins (I/O
is then written into the location specified on the address pins (A
through A
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins will appear on the I/O pins.
Deselected (CE HIGH)
Outputs are disabled (OE HIGH)
When the write operation is active(CE LOW and WE LOW)
18
San Jose
).
http://www.cypress.com.
,
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CA 95134-1709
0
0
1
2
3
4
5
6
7
through I/O
[1]
CY62148DV30
Static RAM
7
) are placed in a
• 408-943-2600
0
through I/O
Page 1 of 13
) in portable
7
0
[+] Feedback
)

Related parts for CY62148DV30LL-55SXI

CY62148DV30LL-55SXI Summary of contents

Page 1

... Note 1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” on Cypress Semiconductor Corporation Document Number : 38-05341 Rev. *F  4-Mbit (512K x 8) MoBL Functional Description The CY62148DV30 is a high-performance CMOS static RAM organized as 512K words by 8 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ ...

Page 2

Contents Pin Configuration ............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 5 ...

Page 3

... Pin Configuration Product Portfolio Product Range Min CY62148DV30LL Industrial 2.2 Note 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V Document Number : 38-05341 Rev. *F 32-pin SOIC Pinout Top View I I/O I I/O I I/O I/O ...

Page 4

... Full device AC operation assumes a 100 s ramp time from Document Number : 38-05341 Rev input voltage Output current into outputs (LOW) .............................. 20 mA Static discharge voltage........................................... > 2001V (per MIL-STD-883, method 3015) Latch-up current ..................................................... > 200 mA Operating Range Product + 0.3 V CC(max) CY62148DV30LL + 0.3 V CC(max) Test Conditions = –0 2. –1 2. ...

Page 5

Capacitance [6] Parameter Description C Input capacitance IN C Output capacitance OUT Thermal Resistance [6] Parameter Description  Thermal resistance  JA (Junction to ambient)  Thermal resistance (Junction to JC case) AC Test Loads and Waveforms ...

Page 6

... HZOE HZCE HZWE 12. The internal write time of the memory is defined by the overlap of WE terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 13. Device is continuously selected. OE ...

Page 7

Switching Waveforms (continued) Figure 2. Read Cycle No. 2 (OE Controlled) ADDRESS CE t ACE OE t LZOE HIGH IMPEDANCE DATA OUT t LZCE SUPPLY CURRENT Figure 3. Write Cycle No. 1 (WE Controlled) ADDRESS CE ...

Page 8

Switching Waveforms (continued) Figure 4. Write Cycle No. 2 (CE Controlled) ADDRESS DATA I/O Figure 5. Write Cycle No. 3 (WE Controlled, OE LOW) ADDRESS NOTE 22 DATA I/O t HZWE Truth ...

Page 9

... Ordering Information Speed Ordering Code (ns) 55 CY62148DV30LL-55SXI Contact your local Cypress sales representative for availability of these parts Ordering Code Definition D V30 LL 621 Document Number : 38-05341 Rev. *F Package Package Type Diagram 51-85081 32-pin SOIC (Pb-free) I Temperature Grade Industrial Package Type pin SOIC (Pb-free) ...

Page 10

Package Diagrams MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. Document Number : 38-05341 Rev. *F ...

Page 11

... Acronyms Acronym Description CMOS complementary metal oxide semiconductor I/O input/output MoBL more battery life SOIC small-outline integrated circuit SRAM static random access memory Document Conventions Units of Measure Symbol Unit of Measure ns nano seconds V volts µA micro amperes mA milli amperes pF pico Farad °C ...

Page 12

Document History Page Document Title:CY62148DV30, 4-Mbit (512K x 8) MoBL Document Number: 38-05341 REV. ECN NO. Issue Date ** 127480 06/17/03 *A 131041 01/23/04 *B 222180 See ECN *C 498575 See ECN *D 729917 See ECN *E 2896036 03/19/10 *F ...

Page 13

... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...

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