CY62128ELL-55ZAXE Cypress Semiconductor Corp, CY62128ELL-55ZAXE Datasheet - Page 8

• Manufacturer Part Number: CY62128ELL-55ZAXE
• Description: IC SRAM 1MBIT 55NS 32STSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY62128ELL-55ZAXE

• Memory Size: 1M (128K x 8)
• Package / Case: 32-sTSOP
• Format - Memory: RAM
• Memory Type: SRAM
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Access Time: 55 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Current: 35 mA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Switching Waveforms
Document #: 38-05485 Rev. *H
Notes
24. CE is the logical combination of CE
25. The internal Write time of the memory is defined by the overlap of WE, CE = V
26. Data I/O is high impedance if OE = V
27. If CE
28. During this period, the I/Os are in output state and input signals must not be applied.
ADDRESS
ADDRESS
DATA I/O
terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
DATA I/O
1
goes HIGH or CE
WE
WE
CE
CE
NOTE 28
2
goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
t
SA
Figure 4. Write Cycle No. 2 (CE1 or CE2 Controlled)
1
(continued)
Figure 5. Write Cycle No. 3 (WE Controlled, OE LOW)
and CE
IH
.
t
HZWE
2
. When CE
t
SA
1
is LOW and CE
t
AW
t
AW
t
SCE
t
t
WC
2
WC
t
is HIGH, CE is LOW; when CE
PWE
IL
t
. All signals must be ACTIVE to initiate a write and any of these signals can
PWE
t
DATA VALID
DATA VALID
t
SCE
SD
t
SD
[24, 25, 26, 27]
1
is HIGH or CE
[24, 27]
t
HD
t
t
HA
LZWE
t
HA
t
HD
2
is LOW, CE is HIGH.
CY62128E MoBL
Page 8 of 14
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