CY7C024AV-25AC Cypress Semiconductor Corp, CY7C024AV-25AC Datasheet
CY7C024AV-25AC
Specifications of CY7C024AV-25AC
Available stocks
Related parts for CY7C024AV-25AC
CY7C024AV-25AC Summary of contents
Page 1
... Dual-Port Static RAM Features • True dual-ported memory cells which allow simulta- neous access of the same memory location • 4/8/16K × 16 organization (CY7C024AV/025AV/026AV) • 4/8K × 18 organization (CY7C0241AV/0251AV) • 16K × 18 organization (CY7C036AV) • 0.35-micron CMOS for optimum speed/power • ...
Page 2
... I/O 13L 8 GND 9 I/O 10 14L I/O 11 15L GND Notes the CY7C025AV. 12L the CY7C025AV. 12R Document #: 38-06052 Rev. *B 100-Pin TQFP Top View 100 CY7C024AV (4K × 16) CY7C025AV (8K × 16 CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV INT 65 L BUSY 64 L GND 63 M/S 62 BUSY 61 R INT ...
Page 3
... I/O3R 18 I/O4R 19 I/O5R 20 I/O6R Notes the CY7C0251AV. 12L the CY7C0251AVC. 12R Document #: 38-06052 Rev. *B Top View 100-Pin TQFP CY7C0241AV (4K × 18) CY7C0251AV (8K × 18 CY7C026AV (16K × 16 CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV INT 65 L BUSY 64 L GND 63 M/S 62 BUSY 61 R INT A6L 71 A5L 70 A4L 69 A3L 68 A2L ...
Page 4
... SB3 (Both ports CMOS Level) Document #: 38-06052 Rev. *B 100-Pin TQFP Top View 100 CY7C036AV (16K × 18 CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV -20 20 120 35 10 CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV 13L INT L 65 BUSY 64 L GND 63 M/S 62 BUSY 61 R INT 13R CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV -25 25 115 30 10 Unit Page ...
Page 5
... Power. Ground. No Connect. Architecture The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV/ 036AV consist of an array of 4K, 8K, and 16K words of 16 and 18 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory ...
Page 6
... The upper two memory locations may be used for message passing. The highest memory location (FFF for the CY7C024AV/41AV, 1FFF for the CY7C025AV/51AV, 3FFF for the CY7C026AV/36AV) is the mailbox for the right port and the second-highest memory location (FFE for the CY7C024AV/ 41AV, 1FFE for the CY7C025AV/51AV, 3FFE for the CY7C026AV/36AV) is the mailbox for the left port ...
Page 7
... Semaphore-free 1 0 Right port has semaphore token 1 1 Semaphore free 0 1 Left port has semaphore token 1 1 Semaphore-free CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV I/O –I/O Operation 0 8 High Z Deselected: Power-Down High Z Deselected: Power-Down High Z Write to Upper Byte Only Data In Write to Lower Byte Only ...
Page 8
... MAX Ind. Com’l. L [15] Ind. Com’l. [15] Ind. Com’l. [16] [15] MAX Ind. Description Test Conditions MHz 3.3V CC CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV [14] ................................. –0. Ambient Temperature +70 C [15] – +85 C -20 -25 Typ. Max. Min. Typ. 2.4 2.4 0.4 2.0 2.0 0.8 –10 10 –10 – ...
Page 9
... TH OUTPUT C = 30pF (b) Thévenin Equivalent (Load 1) ALL INPUT PULSES 3.0V 90% 90% 10% GND 3 ns [18] Description Min. is less than t HZCE LZCE CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV 3.3V OUTPUT 1.4V TH (c) Three-State Delay(Load 2) (Used for HZWE including scope and jig) 10 CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV -20 -25 Max. Min. Max ...
Page 10
... BDD 26 GND This parameter is guaranteed but not tested Document #: 38-06052 Rev. *B [18] (continued) Description Timing and after V reaches the CC Parameter ICC DR1 –t (actual –t (actual). WDD PWE DDD SD CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV -20 -25 Min. Max. Min. Max ...
Page 11
... IL IL Document #: 38-06052 Rev. *B [27, 28, 29 [27, 30, 31] t ACE t DOE t LZOE t LZCE LZCE t ABE t ACE t LZCE and This waveform cannot be used for semaphore reads SEM = access semaphore SEM = CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV t OHA DATA VALID t HZCE t HZOE DATA VALID OHA t HZCE t HZCE . IL Page ...
Page 12
... Document #: 38-06052 Rev. *B [32, 33, 34, 35 [35] t PWE [38] t HZWE t SD [32, 33, 34, 40 SCE LOW CE or SEM and a LOW UB or LB. PWE PWE , SEM = CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV [38] t HZOE LZWE NOTE allow the I/O drivers to turn off and data to be placed on HZWE SD . PWE Page ...
Page 13
... SPS Document #: 38-06052 Rev. *B [41 SCE t SD DATA VALID PWE t SWRD t SOP WRITE CYCLE [42, 43, 44] MATCH t SPS MATCH = CE = HIGH CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV t t SAA OHA VALID ADRESS t ACE t SOP DATA VALID OUT t DOE READ CYCLE Page ...
Page 14
... Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 45 LOW Document #: 38-06052 Rev. *B CY7C0241AV/0251AV/036AV [45 MATCH t PWE t SD VALID MATCH t BLA t PWE CY7C024AV/025AV/026AV BHA t BDD t DDD VALID t WDD Page ...
Page 15
... BUSY will be asserted. PS Document #: 38-06052 Rev. *B [46] ADDRESS MATCH BLC ADDRESS MATCH BLC [46 ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV t BHC t BHC Page ...
Page 16
... Left Side Clears INT L : ADDRESS R INT L Notes: 47. t depends on which enable pin ( depends on which enable pin (CE INS INR Document #: 38-06052 Rev [47 [48] [48] t INR t WC [47 [48] [48] t INR ) is deasserted first R asserted last CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV t RC READ 7FFF (OR 1/3FFF READ 7FFE OR 1/3FFE) Page ...
Page 17
... Ordering Information 4K x16 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 20 CY7C024AV-20AC 25 CY7C024AV-25AC 8K x16 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 20 CY7C025AV-20AC 25 CY7C025AV-25AC CY7C025AV-25AI 16K x18 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 20 CY7C026AV-20AC 25 CY7C026AV-25AC CY7C026AV-25AI 4K x18 3.3V Asynchronous Dual-Port SRAM Speed ...
Page 18
... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV ...
Page 19
... Document History Page Document Title: CY7C024AV/CY7C025AV/CY7C026AV/CY7C0241AV/CY7C0251AV/CY7C036AV 3.3V 4K/8K/16K x 16/18 Dual Port Static RAM Document Number: 38-06052 REV. ECN NO. Issue Date ** 110204 11/11/01 *A 122302 12/27/02 *B 128958 9/03/03 Document #: 38-06052 Rev. *B Orig. of Change SZV Change from Spec number: 38-00838 to 38-06052 RBI Power up requirements added to Maximum Ratings Information ...