CY7C006A-20JC Cypress Semiconductor Corp, CY7C006A-20JC Datasheet
CY7C006A-20JC
Specifications of CY7C006A-20JC
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CY7C006A-20JC Summary of contents
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... Semaphores included to permit software handshaking between ports • INT flags for port-to-port communication • Pin select for Master or Slave • Commercial temperature range • Available in 68-pin PLCC (CY7C006A, CY7C007A and CY7C017A), 64-pin TQFP (CY7C006A), and in 80-pin TQFP (CY7C007A and CY7C016A) • Pb-Free packages available I/O ...
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... I/O 4R I Notes: 5. This pin is I/O for CY7C017A only connect pin for 16K devices. 14 Document #: 38-06045 Rev. *D 68-Pin PLCC Top View GND 14 I I/O CY7C006A (16K CY7C007A (32K x 8) GND 18 CY7C017A (32K 80-Pin TQFP ...
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... Maximum Access Time (ns) Typical Operating Current (mA) Typical Standby Current for I (mA) (Both Ports TTL Level) SB1 Typical Standby Current for I (mA) (Both Ports CMOS Level) SB3 Document #: 38-06045 Rev. *D 64-Pin TQFP Top View CY7C006A (16K CY7C006A CY7C007A CY7C016A CY7C017A [1] -12 12 195 55 0 ...
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... An automatic power-down feature is controlled independently on each port by a Chip Select (CE) pin. The CY7C006A, CY7C007A, and CY7C017A are available in 68-pin PLCC packages, the CY7C006A is also available in 64-pin TQFP, and the CY7C007A and CY7C016A are also available in 80-pin TQFP packages. Write Operation Data must be set up for a duration R/W in order to guarantee a valid write ...
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... The operation of the interrupts and their interaction with Busy are summarized in Table 2. Busy The CY7C006A, CY7C007A, CY7C016A and CY7C017A provide on-chip arbitration to resolve simultaneous memory location access (contention). If both ports’ CEs are asserted and an address match occurs within t PS logic will determine which port has access ...
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... V = 5.0V CC (except output enable means no address or control lines change. This applies only to inputs at CMOS level CY7C006A/CY7C007A CY7C016A/CY7C017A [8] .........................................–0.5V to +7.0V Ambient Temperature ° ° 5V ± 10 +70 C CY7C006A CY7C007A CY7C016A CY7C017A -15 -20 Min. Typ. Max. Min. Typ. 2.4 2.4 0.4 2.2 2.2 0.8 – ...
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... Note: 11. Test Conditions pF. Document #: 38-06045 Rev 250Ω TH OUTPUT (b) Thévenin Equivalent (Load 1) [11] 3.0V GND = 1. Capacitance (pF) (b) Load Derating Curve CY7C006A/CY7C007A CY7C016A/CY7C017A 5V OUTPUT 1.4V TH (c) Three-State Delay (Load 2) (Used for HZWE including scope and jig) ALL INPUT PULSES 90% 90% 10% 10% ≤ ...
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... For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 18. Test conditions used are Load 2. 19. For 15 ns industrial parts t Min. is 0.5 ns. HD Document #: 38-06045 Rev. *D CY7C006A/CY7C007A CY7C016A/CY7C017A [12] CY7C006A CY7C007A CY7C016A CY7C017A [1] –12 –15 Min. Max. ...
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... SEM Address Access Time SAA Data Retention Mode The CY7C006A, CY7C007A, CY7C016A, and CY7C017A are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip Enable (CE) must be held HIGH during data retention, ...
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... ADDRESS CE DATA OUT Notes: 25. Address valid prior to or coincident with CE transition LOW. 26. To access RAM SEM = access semaphore Document #: 38-06045 Rev. *D [22, 25, 26] t ACE t DOE t LZOE t LZCE LZCE t ABE t ACE t LZCE , SEM = CY7C006A/CY7C007A CY7C016A/CY7C017A t HZCE t HZOE DATA VALID OHA t HZCE Page ...
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... HZWE t SD [27, 28, 29, 34 SCE LOW CE or SEM. PWE . HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be SD CY7C006A/CY7C007A CY7C016A/CY7C017A [32] t HZOE LZWE NOTE allow the I/O drivers to turn off and data ...
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... SPS Document #: 38-06045 Rev. *D [35 SCE t SD DATA VALID PWE t SWRD t SOP WRITE CYCLE [36, 37, 38] MATCH t SPS MATCH = CE = HIGH CY7C006A/CY7C007A CY7C016A/CY7C017A OHA VALID ADRESS t ACE t SOP DATA VALID OUT t DOE READ CYCLE Page ...
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... Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 39 LOW Document #: 38-06045 Rev. *D [39 MATCH t PWE t SD VALID MATCH t BLA t PWE CY7C006A/CY7C007A CY7C016A/CY7C017A BHA t BDD t DDD VALID t WDD Page ...
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... BUSY will be asserted. PS Document #: 38-06045 Rev. *D [40] ADDRESS MATCH BLC ADDRESS MATCH BLC [40 ADDRESS MATCH ADDRESS MISMATCH t t BLA BHA ADDRESS MATCH ADDRESS MISMATCH t t BLA BHA CY7C006A/CY7C007A CY7C016A/CY7C017A t BHC t BHC Page ...
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... Notes: 41. t depends on which enable pin ( depends on which enable pin (CE INS INR Document #: 38-06045 Rev WRITE 7FFF [41 [42] [42] t INR t WC WRITE 7FFE [41 [42] [42] t INR ) is deasserted first R asserted last CY7C006A/CY7C007A CY7C016A/CY7C017A t RC READ 7FFF t RC READ 7FFE Page ...
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... No change. Left port has no write access to semaphore 0 1 Left port obtains semaphore token 1 1 Semaphore free 1 0 Right port has semaphore token 1 1 Semaphore free 0 1 Left port has semaphore token 1 1 Semaphore free CY7C006A/CY7C007A CY7C016A/CY7C017A Operation Right Port R 0R–14R ...
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... Ordering Information 16K x8 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 12 CY7C006A-12AC CY7C006A-12JC 15 CY7C006A-15AC CY7C006A-15AXC CY7C006A-15JC 20 CY7C006A-20AC CY7C006A-20AXC CY7C006A-20AI CY7C006A-20AXI CY7C006A-20JC CY7C006A-20JXC 32K x8 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 12 CY7C007A-12AC CY7C007A-12JC 15 CY7C007A-15AC CY7C007A-15JC 20 CY7C007A-20AC CY7C007A-20JC CY7C007A-20JXC 16K x9 Asynchronous Dual-Port SRAM Speed ...
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... Package Diagrams 64-Lead Thin Plastic Quad Flat Pack ( 1.4 mm) A65 64-Lead Pb-Free Thin Plastic Quad Flat Pack ( 1.4 mm) A65 Document #: 38-06045 Rev. *D CY7C006A/CY7C007A CY7C016A/CY7C017A 51-85046-*B Page ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 80-Pin Thin Plastic Quad Flat Pack A80 CY7C006A/CY7C007A CY7C016A/CY7C017A 51-85065-*B ...
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... Document History Page Document Title: CY7C006A/CY7C007A/CY7C016A/CY7C017A 32K/16K x 8, 32K/16K x 9 Dual Port Static RAM Document Number: 38-06045 Issue REV. ECN NO. Date ** 110197 09/29/01 *A 122295 12/27/02 *B 237620 See ECN *C 345376 See ECN *D 387333 See ECN Document #: 38-06045 Rev. *D Orig. of Change Description of Change ...