CY7C09089V-12AC Cypress Semiconductor Corp, CY7C09089V-12AC Datasheet - Page 9

• Manufacturer Part Number: CY7C09089V-12AC
• Description: IC SRAM 512KBIT 12NS 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09089V-12AC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 512K (64K x 8)
• Speed: 12ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1175

Switching Waveforms
Bank Select Pipelined Read
-
Left Port Write to Flow-Through Right Port Read
Notes:
Document #: 38-06043 Rev. *A
ADDRESS
20. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this datasheet.
21. OE and ADS = V
22. The same waveforms apply for a right port write to flow-through left port read.
23. CE
24. OE = V
25. It t
ADDRESS
DATA
DATA
ADDRESS
ADDRESS
DATA
ADDRESS
valid until t
DATA
CCS
CE
CE
OUT(B2)
OUT(B1)
0
and ADS = V
CLK
CLK
R/W
CLK
R/W
OUTR
0(B1)
0(B2)
(B1)
IL
(B2)
INL
maximum specified, then data from right port READ is not valid until the maximum specified for t
for the right port, which is being read from. OE = V
L
R
R
R
CCS
L
L
L
(B1)
= ADDRESS
+ t
t
t
t
t
SA
SC
SA
SC
IL
CD1
IL
; CE
; CE
. t
1(B1)
t
t
CWDD
t
SW
1
SA
SD
, CNTEN, and CNTRST = V
A
A
0
, CE
0
(B2)
t
does not apply in this case.
CH2
MATCH
VALID
.
1(B2)
(continued)
[20, 21]
t
t
t
t
SW
SA
t
t
t
t
MATCH
CYC2
CCS
HA
HC
HA
HC
, R/W, CNTEN, and CNTRST = V
t
DC
t
CL2
t
t
t
t
HW
HA
t
HW
HA
HD
A
A
1
1
t
CWDD
IH
t
CD2
.
t
CD1
IH
[22, 23, 24, 25]
t
SC
for the left port, which is being written to.
D
t
0
SC
IH
A
A
.
2
2
t
t
DC
HC
t
HC
t
CD2
MATCH
VALID
NO
D
MATCH
A
A
1
3
t
NO
3
DC
t
t
CKLZ
CKHZ
t
t
CD2
DC
CWDD
CY7C09079V/89V/99V
CY7C09179V/89V/99V
. If t
t
CD1
CCS
D
A
A
4
2
>maximum specified, then data is not
4
t
t
t
CKHZ
CD2
CKLZ
D
3
A
A
Page 9 of 18
VALID
5
t
5
CKLZ
t
t
CKHZ
CD2
D
4