IS61LV12824-10TQ ISSI, Integrated Silicon Solution Inc, IS61LV12824-10TQ Datasheet - Page 8

• Manufacturer Part Number: IS61LV12824-10TQ
• Description: IC SRAM 3MBIT 10NS 100TQFP
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS61LV12824-10TQ

• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Memory Size: 3M (128K x 24)
• Speed: 10ns
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

IS61LV12824
WRITE CYCLE SWITCHING CHARACTERISTICS
8
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
Notes:
1. Test conditions assume signal transition times of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1, CE2 LOW, CE2 HIGH and WE LOW. All signals must be in valid
WC
HA
SD
HD
SCE
SCE
AW
SA
PWE
PWE
HZWE
LZWE
and output loading specified in Figure 1.
states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are
referenced to the rising or falling edge of the signal that terminates the write.
2
1
2
(2)
(2)
Parameter
Write Cycle Time
CE1, CE2 to Write End
CE2 to Write End
Address Setup Time
to Write End
Address Hold from Write End
Address Setup Time
WE Pulse Width (OE = HIGH)
WE Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
Min. Max.
4.5
—
8
7
7
7
0
0
6
6
0
3
-8
3.5
—
—
—
—
—
—
—
—
—
—
—
(1,3)
Integrated Silicon Solution, Inc. — 1-800-379-4774
(Over Operating Range)
Min.
10
—
8
8
8
0
0
8
9
5
0
3
-10
Max.
3.5
—
—
—
—
—
—
—
—
—
—
—
ISSI
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
06/22/05
Rev. D
®