AT49LV040-12TC Atmel, AT49LV040-12TC Datasheet - Page 2

• Manufacturer Part Number: AT49LV040-12TC
• Description: IC FLASH 4MBIT 120NS 32TSOP
• Manufacturer: Atmel

Specifications of AT49LV040-12TC

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 120ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: AT49LV04012TC

To allow for simple in-system reprogrammability, the
AT49BV/LV040 does not require high input voltages for
programming. Three-volt-only commands determine the
read and programming operation of the device. Reading
data out of the device is similar to reading from an EPROM.
Reprogramming the AT49BV/LV040 is performed by eras-
i ng th e e n ti r e f o ur m e ga bi t s of m e m or y a nd th e n
programming on a byte-by-byte basis. The typical byte pro-
gramming time is a fast 30 µs. The end of a program cycle
can be optionally detected by the Data Polling feature.
Block Diagram
Device Operation
READ: The AT49BV/LV040 is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high-
impedance state whenever CE or OE is high. This dual-line
control gives designers flexibility in preventing bus
contention.
ERASURE: Before a byte can be reprogrammed, the 512K
bytes memory array (or 496K bytes if the boot block fea-
tured is used) must be erased. The erased state of the
memory bits is a logical “1”. The entire device can be
erased at one time by using a six-byte software code. The
software chip erase code consists of six-byte load com-
mands to specific address locations with a specific data
pattern (please refer to “Chip Erase Cycle Waveforms” on
page 8).
After the software chip erase has been initiated, the device
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is t
been enabled, the data in the boot sector will not be
erased.
2
AT49BV/LV040
EC
. If the boot block lockout feature has
ADDRESS
INPUTS
GND
VCC
WE
OE
CE
OE, CE, AND WE
Y DECODER
X DECODER
LOGIC
Once the end of a byte program cycle has been detected, a
new access for a read or program can begin. The typical
number of program and erase cycles is in excess of 10,000
cycles.
The optional 16K bytes boot block section includes a repro-
gramming write lockout feature to provide data integrity.
The boot sector is designed to contain user-secure code,
and when the feature is enabled, the boot sector is perma-
nently protected from being reprogrammed.
BYTE PROGRAMMING: Once the memory array is
erased, the device is programmed (to a logical “0”) on a
byte-by-byte basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can con-
vert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a four-bus cycle
operation (please refer to the Command Definitions table).
The device will automatically generate the required internal
program pulses.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified t
time. The Data Polling feature may also be used to indicate
the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 16K bytes. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
DATA INPUTS/OUTPUTS
BLOCK (16K BYTES)
OPTIONAL BOOT
INPUT/OUTPUT
MAIN MEMORY
(496K BYTES)
DATA LATCH
Y-GATING
I/O7 - I/O0
BUFFERS
8
7FFFFH
04000H
03FFFH
00000H
BP
cycle