AT26DF081A-MU Atmel, AT26DF081A-MU Datasheet - Page 8

• Manufacturer Part Number: AT26DF081A-MU
• Description: IC FLASH 8MBIT 70MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT26DF081A-MU

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 8M (4096 pages x 256 bytes)
• Speed: 70MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AT26DF081-MU; AT26DF081-MU

7. Read Commands
7.1
Figure 7-1.
8
Read Array
AT26DF081A
SCK
SO
CS
Read Array – 0Bh Opcode
SI
MSB
HIGH-IMPEDANCE
0
The Read Array command can be used to sequentially read a continuous stream of data from
the device by simply providing the SCK signal once the initial starting address has been speci-
fied. The device incorporates an internal address counter that automatically increments on every
clock cycle.
Two opcodes, 0Bh and 03h, can be used for the Read Array command. The use of each opcode
depends on the maximum SCK frequency that will be used to read data from the device. The
0Bh opcode can be used at any SCK frequency up to the maximum specified by f
opcode can be used for lower frequency read operations up to the maximum specified by f
To perform the Read Array operation, the CS pin must first be asserted and the appropriate
opcode (0Bh or 03h) must be clocked into the device. After the opcode has been clocked in, the
three address bytes must be clocked in to specify the starting address location of the first byte to
read within the memory array. If the 0Bh opcode is used, then one don't care byte must also be
clocked in after the three address bytes.
After the three address bytes (and the one don't care byte if using opcode 0Bh) have been
clocked in, additional clock cycles will result in serial data being output on the SO pin. The data
is always output with the MSB of a byte first. When the last byte (0FFFFFh) of the memory array
has been read, the device will continue reading back at the beginning of the array (000000h).
No delays will be incurred when wrapping around from the end of the array to the beginning
of the array.
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-imped-
ance state. The CS pin can be deasserted at any time and does not require that a full byte
of data be read.
0
0
1
0
2
OPCODE
0
3
1
4
0
5
1
6
1
7
MSB
A
8
A
9
ADDRESS BITS A23-A0
A
10 11
A
A
12
A
A
29 30
A
A
31 32
MSB
X
X
33
DON'T CARE
X
34
X
35
X
36
X
37 38
X
X
39
MSB
D
40
D
41
DATA BYTE 1
D
42 43
D
D
44
D
45
D
46
D
47 48
MSB
D
D
3600G–DFLASH–06/09
SCK
. The 03h
RDLF
.