AT26DF161A-MU Atmel, AT26DF161A-MU Datasheet - Page 26

• Manufacturer Part Number: AT26DF161A-MU
• Description: IC FLASH 16MBIT 70MHZ 8QFN
• Manufacturer: Atmel

Specifications of AT26DF161A-MU

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 16M (8192 pages x 256 bytes)
• Speed: 70MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-VFQFN, 8-VFQFPN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.2
26
Write Status Register
AT26DF161A
The Write Status Register command is used to modify the SPRL bit of the Status Register
and/or to perform a Global Protect or Global Unprotect operation. Before the Write Status Regis-
ter command can be issued, the Write Enable command must have been previously issued to
set the WEL bit in the Status Register to a logical “1”.
To issue the Write Status Register command, the CS pin must first be asserted and the opcode
of 01h must be clocked into the device followed by one byte of data. The one byte of data con-
sists of the SPRL bit value, a don’t care bit, four data bits to denote whether a Global Protect or
Unprotect should be performed, and two additional don’t care bits (see
tional data bytes that are sent to the device will be ignored. When the CS pin is deasserted, the
SPRL bit in the Status Register will be modified, and the WEL bit in the Status Register will be
reset back to a logical “0”. The values of bits 5, 4, 3, and 2 and the state of the SPRL bit before
the Write Status Register command was executed (the prior state of the SPRL bit) will determine
whether or not a Global Protect or Global Unprotect will be perfomed. Please refer to the “Global
Protect/Unprotect” section on
The complete one byte of data must be clocked into the device before the CS pin is deasserted;
otherwise, the device will abort the operation, the state of the SPRL bit will not change, no
potential Global Protect or Unprotect will be performed, and the WEL bit in the Status Register
will be reset back to the logical “0” state.
If the WP pin is asserted, then the SPRL bit can only be set to a logical “1”. If an attempt is made
to reset the SPRL bit to a logical “0” while the WP pin is asserted, then the Write Status Register
command will be ignored, and the WEL bit in the Status Register will be reset back to the logical
“0” state. In order to reset the SPRL bit to a logical “0”, the WP pin must be deasserted.
Table 10-2.
Figure 10-2. Write Status Register
SPRL
Bit 7
Write Status Register Format
SCK
SO
CS
Bit 6
SI
X
Bit 5
page 18
HIGH-IMPEDANCE
MSB
0
0
0
1
0
2
OPCODE
Global Protect/Unprotect
for more details.
0
3
Bit 4
0
4
0
5
0
6
1
7
MSB
D
8
Bit 3
STATUS REGISTER IN
X
9
D
10 11
D
D
12
Bit 2
D
13
X
14 15
X
Table
Bit 1
X
10-2). Any addi-
3640D–DFLASH–8/09
Bit 0
X