CY7C019V-15AC Cypress Semiconductor Corp, CY7C019V-15AC Datasheet
CY7C019V-15AC
Specifications of CY7C019V-15AC
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CY7C019V-15AC Summary of contents
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... BUSY is an output in master mode and an input in slave mode. For the most recent information, visit the Cypress web site at www.cypress.com Cypress Semiconductor Corporation Document #: 38-06044 Rev. *B • Fully asynchronous operation • Automatic power-down • Expandable data bus to 16/18 bits or more using Mas- ter/Slave chip select when using more than one device • ...
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... Two ports are provided permitting independent, asynchronous ac- cess for reads and writes to any location in memory. The de- vices can be utilized as standalone 8/9-bit dual-port static RAMs or multiple devices can be combined in order to function as a 16/18-bit or wider master/slave dual-port static RAM ...
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... Typical Standby Current for I (mA) SB1 (Both ports TTL level) Typical Standby Current for SB3 (Both ports CMOS level) Note: 5. This pin is NC for CY7C018V. Document #: 38-06044 Rev. *B 100-Pin TQFP (Top View CY7C019V (128K x 9) CY7C018V (64K CY7C008V/009V CY7C018V/019V -15 15 125 CY7C008V/009V CY7C018V/019V ...
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... DC Voltage Applied to Outputs in High Z State............................–0. Note: 6. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 7. Industrial parts are available in CY7C009V and CY7C019V only. Document #: 38-06044 Rev. *B Chip Enable (CE is LOW when CE Read/Write Enable Output Enable Address (A – ...
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Electrical Characteristics Over the Operating Range Parameter Description V Output HIGH Voltage ( Output LOW Voltage ( Input HIGH Voltage IH V Input LOW Voltage IL I Input Leakage Current IX I Output Leakage Current OZ ...
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Switching Characteristics Over the Operating Range Parameter Description READ CYCLE t Read Cycle Time RC t Address to Data Valid AA t Output Hold From Address Change OHA [11 LOW to Data Valid ACE t OE LOW to ...
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Switching Characteristics Over the Operating Range Parameter Description [16] INTERRUPT TIMING t INT Set Time INS t INT Reset Time INR SEMAPHORE TIMING t SEM Flag Update Pulse (OE or SEM) SOP t SEM Flag Write to Read Time SWRD ...
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Switching Waveforms Read Cycle No.1 (Either Port Address Access) ADDRESS t OHA DATA OUT PREVIOUS DATA VALID Read Cycle No.2 (Either Port CE/OE Access DATA OUT I CC CURRENT I SB [19, 21, 22, 23] Read Cycle No. ...
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Switching Waveforms (continued) Write Cycle No. 1: R/W Controlled Timing ADDRESS OE [28 R/W NOTE 30 DATA OUT DATA IN Write Cycle No Controlled Timing ADDRESS [28 R/W DATA IN Notes: 24. ...
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Switching Waveforms (continued) Semaphore Read After Write Timing, Either Side A –A VALID ADRESS 0 2 SEM I R/W OE Timing Diagram of Semaphore Contention A – R/W L SEM L A – ...
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Switching Waveforms (continued) Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 36 LOW. ...
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Switching Waveforms (continued) Busy Timing Diagram No. 1 (CE Arbitration) CE Valid First: L ADDRESS L BUSY R CE ValidFirst: R ADDRESS L BUSY L Busy Timing Diagram No. 2 (Address Arbitration) ...
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Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INT : R ADDRESS WRITE FFFF (1FFFF for CY7C009V/19V R/W L INT R [39] t INS Right Side Clears INT : R ADDRESS R/W R ...
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... HIGH during SEM LOW). A address. OE and R/W are used in the same manner as a normal memory access. When writing or reading a semaphore, the other address pins have no effect. When writing to the semaphore, only I/O written to the left port of an available semaphore, a one will appear at the same semaphore address on the right port ...
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Table 1. Non-Contending Read/Write Inputs CE R/W OE SEM Table 2. Interrupt Operation ...
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... Speed (ns) Ordering Code 15 CY7C009V-15AC 20 CY7C009V-20AC CY7C009V-20AI 25 CY7C009V-25AC 128K x9 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C019V-15AC 20 CY7C019V-20AC CY7C019V-20AI 25 CY7C019V-25AC Document #: 38-06044 Rev. *B Package Name Package Type A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack ...
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... Document #: 38-06044 Rev. *B © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...
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Document Title: CY7C008V/009V, CY7C018V/019V 3.3V 64K/128K X 8/9 Dual Port Static RAM Document Number: 38-06044 Issue REV. ECN NO. Date ** 110192 09/29/01 *A 113541 04/15/02 *B 122294 12/27/02 Document #: 38-06044 Rev. *B Orig. of Change Description of Change ...