CY7C024-25JXCT Cypress Semiconductor Corp, CY7C024-25JXCT Datasheet - Page 12

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CY7C024-25JXCT

Manufacturer Part Number
CY7C024-25JXCT
Description
IC SRAM 64KBIT 25NS 84PLCC
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C024-25JXCT

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Asynchronous
Memory Size
64K (4K x 16)
Speed
25ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
84-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C024-25JXCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Document #: 38-06035 Rev. *C
Switching Waveforms
Notes:
27. R/W must be HIGH during all address transitions.
28. A write occurs during the overlap (t
29. t
30. If OE is LOW during a R/W-controlled write cycle, the write pulse width must be the larger of t
31. To access RAM, CE = V
32. To access upper byte, CE = V
33. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
34. During this period, the I/O pins are in the output state, and input signals must not be applied.
35. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
Write Cycle No. 2: CE Controlled Timing
Write Cycle No. 1: R/W Controlled Timing
CE
DATA OUT
ADDRESS
ADDRESS
placed on the bus for the required t
the specified t
To access lower byte, CE = V
CE
HA
DATA IN
DATA IN
[31,32]
is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
[31,32]
R/W
R/W
OE
PWE
.
IL
, SEM = V
IL
, LB = V
IL
, UB = V
(continued)
t
t
SA
SA
IH
SD
SCE
NOTE 34
IL
.
, SEM = V
. If OE is HIGH during an R/W-controlled write cycle, this requirement does not apply and the write pulse can be as short as
IL
or t
, SEM = V
PWE
) of a LOW CE or SEM and a LOW UB or LB.
IH
.
IH
.
t
[27, 28, 29, 35]
HZWE
[27, 28, 29, 30]
[33]
t
t
AW
AW
t
t
WC
WC
t
t
SCE
PWE
[30]
t
t
SD
SD
PWE
or (t
HZWE
t
t
HA
HA
+ t
SD
t
t
HD
HD
) to allow the I/O drivers to turn off and data to be
t
LZWE
CY7C024/0241
CY7C025/0251
t
HZOE
NOTE 34
[33]
Page 12 of 21
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