CY7C1520AV18-200BZC Cypress Semiconductor Corp, CY7C1520AV18-200BZC Datasheet - Page 5

• Manufacturer Part Number: CY7C1520AV18-200BZC
• Description: IC SRAM 72MBIT 200MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1520AV18-200BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 72M (2M x 36)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Pin Definitions
Document Number: 001-06982 Rev. *F
Pin Name
DQ
LD
BWS
BWS
BWS
BWS
A, A0
R/W
C
C
K
K
CQ
CQ
ZQ
[x:0]
0
1
2
3
,
,
,
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Output Clock CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock
Output Clock CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock
Input Clock
Input Clock
Input Clock
Input Clock
Input-
Input-
Input-
Input-
Input
I/O-
I/O
Data Input Output Signals. Inputs are sampled on the rising edge of K and K clocks during valid write
operations. These pins drive out the requested data when the read operation is active. Valid data is driven
out on the rising edge of both the C and C clocks during read operations or K and K when in single clock
mode. When read access is deselected, Q
CY7C1518AV18 − DQ
CY7C1520AV18 − DQ
Synchronous load. This input is brought LOW when a bus cycle sequence is defined. This definition
includes address and read/write direction. All transactions operate on a burst of 2 data.
Byte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and K clocks during
write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered.
CY7C1518AV18 − BWS
CY7C1520AV18 − BWS
D
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
Address Inputs. These address inputs are multiplexed for both read and write operations. Internally, the
device is organized as 4 M × 18 (2 arrays each of 2 M × 18) for CY7C1518AV18, and 2 M × 36 (2 arrays
each of 1 M × 36) for CY7C1520AV18.
CY7C1518AV18 – A0 is the input to the burst counter. These are incremented in a linear fashion internally.
22 address inputs are needed to access the entire memory array.
CY7C1520AV18 – A0 is the input to the burst counter. These are incremented in a linear fashion internally.
21 address inputs are needed to access the entire memory array. All the address inputs are ignored when
the appropriate port is deselected.
Synchronous Read or Write Input. When LD is LOW, this input designates the access type (read when
R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold times
around edge of K.
Positive Input Clock for Output Data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board back
to the controller. See application example for further details.
Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board back
to the controller. See application example for further details.
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q
edge of K.
Negative Input Clock Input. K is used to capture synchronous data being presented to the device and
to drive out data through Q
for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timing
for the echo clocks is shown in the AC Timing table.
for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timing
for the echo clocks is shown in the AC Timing table.
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ, and Q
between ZQ and ground. Alternatively, this pin can be connected directly to V
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
[35:27]
.
[17:0]
[35:0]
0
0
controls D
controls D
[x:0]
[x:0]
when in single clock mode.
[x:0]
output impedance are set to 0.2 x RQ, where RQ is a resistor connected
[8:0]
when in single clock mode. All accesses are initiated on the rising
[8:0]
, BWS
and BWS
[x:0]
Pin Description
1
controls D
are automatically tristated.
1
controls D
[17:9]
, BWS
[17:9].
2
controls D
DDQ
CY7C1518AV18
CY7C1520AV18
[26:18]
, which enables the
and BWS
Page 5 of 28
3
controls
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