XC17S20XLVO8C Xilinx Inc, XC17S20XLVO8C Datasheet - Page 2

• Manufacturer Part Number: XC17S20XLVO8C
• Description: IC 3V PROM SER 200K 8-TSOP
• Manufacturer: Xilinx Inc

Specifications of XC17S20XLVO8C

• Programmable Type: OTP
• Memory Size: 200kb
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Pin Description
Pins not listed are in
Table 1: Spartan PROM Pinouts
Pinout Diagrams
DS030 (v1.12) June 20, 2008
Product Specification
(OE/RESET)
RESET/OE
Pin Name
DATA
GND
CLK
V
CE
CC
OE/RESET
DATA(D0)
R
CLK
NC
NC
NC
NC
NC
NC
CE
VOIC/TSOP (VO8)
PDIP (PD8) and
Table 1
1
2
3
4
5
6
7
8
9
10
8-pin
7, 8
Product Obsolete or Under Obsolescence
1
2
3
4
5
SO20
View
Top
are "no connects."
Spartan/XL Family One-Time Programmable Configuration PROMs (XC17S00/XL)
20
19
18
17
16
15
14
13
12
11
(SO20)
DS030_04_110102
20-pin
18, 20
SOIC
10
11
1
3
8
VCC
NC
VCC
NC
NC
NC
NC
NC
NC
GND
Data output, High-Z state when either CE or OE are inactive. During
programming, the DATA pin is I/O. Note that OE can be programmed to be either
active High or active Low.
Each rising edge on the CLK input increments the internal address counter, if both
CE and OE are active.
When High, this input holds the address counter reset and puts the DATA output
in a high-impedance state. The polarity of this input pin is programmable as either
RESET/OE or OE/RESET. To avoid confusion, this document describes the pin
as RESET/OE, although the opposite polarity is possible on all devices. When
RESET is active, the address counter is held at zero, and the DATA output is in a
high-impedance state. The polarity of this input is programmable. The default is
active High RESET, but the preferred option is active Low RESET, because it can
be driven by the FPGAs INIT pin.
The polarity of this pin is controlled in the programmer interface. This input pin is
easily inverted using the Xilinx HW-130 programmer software. Third-party
programmers have different methods to invert this pin.
When High, this pin disables the internal address counter, puts the DATA output
in a high-impedance state, and forces the device into low-I
GND is the ground connection.
The V
www.xilinx.com
CC
pins are to be connected to the positive voltage supply.
OE/RESET
DATA(D0)
Pin Description
CLK
CE
1
2
3
4
PD8/PDG8
VO8/VOG8
Top View
SOG8
CC
8
7
6
5
DS030_05_060508
standby mode.
VCC
VCC
NC
GND
2