XC18V02VQ44I Xilinx Inc, XC18V02VQ44I Datasheet - Page 6

• Manufacturer Part Number: XC18V02VQ44I
• Description: IC PROM SER I-TEMP 3.3V 44-VQFP
• Manufacturer: Xilinx Inc

Specifications of XC18V02VQ44I

• Programmable Type: In System Programmable
• Memory Size: 2Mb
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

XC18V00 Series In-System Programmable Configuration PROMs
Table 2: Xilinx FPGAs and Compatible PROMs
Capacity
In-System Programming
In-System Programmable PROMs can be programmed
individually, or two or more can be daisy-chained together
and programmed in-system via the standard 4-pin JTAG
Reliability and Endurance
Xilinx in-system programmable products provide a guaran-
teed endurance level of 20,000 in-system program/erase
cycles and a minimum data retention of 20 years. Each
device meets all functional, performance, and data reten-
tion specifications within this endurance limit.
6
Figure 2: In-System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable
XC3S1500
XC3S2000
XC3S4000
XC3S5000
XC18V512
Device
XC18V04
XC18V02
XC18V01
Devices
Configuration
11,316,864
13,271,936
5,214,784
7,673,024
Bits
Configuration Bits
(a)
4,194,304
2,097,152
1,048,576
524,288
3 of XC18V04 +
2 of XC18V04
3 of XC18V04
XC18V04 +
XC18V00
XC18V01
XC18V01
Solution
www.xilinx.com
1-800-255-7778
protocol as shown in
offers quick and efficient design iterations and eliminates
unnecessary package handling or socketing of devices.
The Xilinx development system provides the programming
data sequence using either Xilinx iMPACT software and a
download cable, a third-party JTAG development system, a
JTAG-compatible board tester, or a simple microprocessor
interface that emulates the JTAG instruction sequence. The
iMPACT software also outputs serial vector format (SVF)
files for use with any tools that accept SVF format and with
automatic test equipment.
All outputs are held in a high-impedance state or held at
clamp levels during in-system programming.
OE/RESET
The ISP programming algorithm requires issuance of a
reset that causes OE to go Low.
External Programming
Xilinx reprogrammable PROMs can also be programmed by
the Xilinx HW-130, Xilinx MultiPRO, or a third-party device
programmer. This provides the added flexibility of using
pre-programmed devices with an in-system programmable
option for future enhancements and design changes.
Design Security
The Xilinx in-system programmable PROM devices incor-
porate advanced data security features to fully protect the
programming data against unauthorized reading via JTAG.
Table 3
shows the security setting available.
(b)
Figure
DS026 (v4.1) December 15, 2003
2. In-system programming
DS026_02_06/1103
Product Specification
R