XC18V04VQ44I Xilinx Inc, XC18V04VQ44I Datasheet - Page 20

• Manufacturer Part Number: XC18V04VQ44I
• Description: IC PROM SER I-TEMP 3.3V 44-VQFP
• Manufacturer: Xilinx Inc

Specifications of XC18V04VQ44I

• Programmable Type: In System Programmable
• Memory Size: 4Mb
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

XC18V00 Series In-System Programmable Configuration PROMs
Revision History
The following table shows the revision history for this document.
20
01/20/00
02/18/00
04/04/00
06/29/00
01/15/01
04/04/01
04/30/01
09/28/01
12/06/01
02/27/02
03/15/02
03/27/02
06/14/02
07/24/02
09/06/02
10/31/02
11/13/00
06/11/01
11/12/01
11/18/02
8/23/99
9/16/99
2/9/99
9/1/99
Date
Version
1.0
1.1
1.2
1.3
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
First publication of this early access specification
Edited text, changed marking, added CF and parallel load
Corrected JTAG order, Security and Endurance data.
Corrected SelectMAP diagram, control inputs, reset polarity. Added JTAG and CF
description, 256 Kbit and 128 Kbit devices.
Added Q44 Package, changed XC18xx to XC18Vxx
Updated JTAG configuration, AC and DC characteristics
Removed stand alone resistor on INIT pin in Figure 5. Added Virtex-E and EM parts to
FPGA table.
Removed XC18V128 and updated format. Added AC characteristics for XC18V01,
XC18V512, and XC18V256 densities.
Features: changed 264 MHz to 264 Mb/s at 33 MHz; AC Spec.: T
CE High time units to µs. Removed Standby Mode statement: “The lower power standby
modes available on some XC18V00 devices are set by the user in the programming
software”. Changed 10,000 cycles endurance to 20,000 cycles.
Updated Figures 5 and 6, added 4.7 resistors. Identification registers: changes ISP
PROM product ID from 06h to 26h.
Updated
table; changed Endurance from 10,000 cycles, 10 years to 20,000, 20 years;
Updated
Under
changed T
AC Characteristics Over Operating Conditions for XC18V01 and
Changed Min values for T
Changed the boundary scan order for the CEO pin in
bits values in the table under
information to the
Updated for Spartan-IIE FPGA family.
Changed
Updated
Updated Xilinx software and modified
Made changes to pages 1-3, 5, 7-11, 13, 14, and 18. Added new
Made additions and changes to
Changed last bullet under
Multiple minor changes throughout, plus the addition of
the deletion of Figure 9.
Made minor change on
Added XC2S400E and XC2S600E to
AC Characteristics Over Operating Conditions for XC18V04 and
Figure
Figure
Table 2
Figure
SCE
from 25 ms to 25 ns.
6, Virtex SelectMAP mode; added XC2V products to Compatible PROM
6: removed Virtex-E in Note 2, fixed SelectMAP mode connections.
7(c).
and
Recommended Operating Conditions
www.xilinx.com
1-800-255-7778
Figure 6
Figure 7
SCE
Connecting Configuration PROMs, page
Xilinx FPGAs and Compatible
from 20 ms to 20 ns and for T
for the Virtex-II Pro family of devices.
Table
(b) and changed orientation of SO20 diagram on page 5.
Table
Figure 6
2.
Revision
2.
and
Figure
Table
Pinout Diagrams, page 4
DS026 (v4.1) December 15, 2003
7.
table.
1, updated the configuration
HCE
PROMs, and added
from 2 ms to 2 µs.
Figure 8
SCE
Product Specification
XC18V512.
units to ns, T
9.
and Figure 9.
XC18V02,
and
HCE
R