XC18V512VQ44I Xilinx Inc, XC18V512VQ44I Datasheet - Page 12

• Manufacturer Part Number: XC18V512VQ44I
• Description: IC PROM SER I-TEMP 3.3V 44-VQFP
• Manufacturer: Xilinx Inc

Specifications of XC18V512VQ44I

• Programmable Type: In System Programmable
• Memory Size: 512kb
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

XC18V00 Series In-System Programmable Configuration PROMs
Reset Activation
On power up, OE/RESET is held low until the XC18V00 is
active (1 ms). OE/RESET is connected to an external 4.7kΩ
resistor to pull OE/RESET HIGH releasing the FPGA INIT
and allowing configuration to begin. If the power drops
below 2.0V, the PROM resets. OE/RESET polarity is not
programmable. See
Standby Mode
The PROM enters a low-power standby mode whenever
CE is asserted High. The address is reset. The output
remains in a high-impedance state regardless of the state of
the OE input. JTAG pins TMS, TDI and TDO can be in a
high-impedance state or High. See
When using the FPGA DONE signal to drive the PROM CE
pin High to reduce standby power after configuration, an
Table 7: Truth Table for PROM Control Inputs
12
Notes:
1.
OE/RESET
3.6V
3.0V
0V
TC = Terminal Count = highest address value. TC + 1 = address 0.
0ms
Control Inputs
High
High
Low
Low
Figure 8: V
1ms
Recommended
Time
V
CCINT
Recommended Operating Range
High
High
Low
Low
CCINT
CE
Figure 8
Time (ms)
Rise
Power-Up Requirements
for power-up requirements.
Table
If address > TC
If address < TC
50ms
7.
Internal Address
Held reset
Held reset
Held reset
(1)
ds026_10_061103
(1)
www.xilinx.com
: don’t change
1-800-255-7778
: increment
external pull-up resistor should be used. Typically a 330Ω
pull-up resistor is used, but refer to the appropriate FPGA
data sheet for the recommended DONE pin pull-up value. If
the DONE circuit is connected to an LED to indicate FPGA
configuration is complete, and also connected to the PROM
CE pin to enable low-power standby mode, then an external
buffer should be used to drive the LED circuit to ensure valid
transitions on the PROMs CE pin. If low-power standby
mode is not required for the PROM, then the CE pin should
be connected to ground.
5V Tolerant I/Os
The I/Os on each re-programmable PROM are fully 5V tol-
erant even through the core power supply is 3.3V. This
allows 5V CMOS signals to connect directly to the PROM
inputs without damage. In addition, the 3.3V V
supply can be applied before or after 5V signals are applied
to the I/Os. In mixed 5V/3.3V/2.5V systems, the user pins,
the core power supply (V
ply (V
makes the PROM devices immune to power supply
sequencing issues.
Customer Control Bits
The XC18V00 PROMs have various control bits accessible
by the customer. These can be set after the array has been
programmed using “Skip User Array” in Xilinx iMPACT soft-
ware. The iMPACT software can set these bits to enable the
optional JTAG read security, parallel configuration mode, or
CF-->D4 pin function. See
CCO
) can have power applied in any order. This
High-Z
High-Z
High-Z
High-Z
Active
DATA
CCINT
Table
DS026 (v4.1) December 15, 2003
), and the output power sup-
Outputs
7.
CEO
High
High
High
High
Low
Product Specification
CCINT
Reduced
Standby
Standby
Active
Active
I
CC
power
R