AD9884AKS-140 Analog Devices Inc, AD9884AKS-140 Datasheet - Page 6

• Manufacturer Part Number: AD9884AKS-140
• Description: IC ANALOG INTRFC 140MSPS 128MQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9884AKS-140

• Rohs Status: RoHS non-compliant
• Display Type: LCD
• Interface: Analog
• Current - Supply: 135mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Configuration: -
• Digits Or Characters: -

AD9884A
Pin Name
INPUTS
R
G
B
HSYNC
COAST
CLAMP
SOGIN
CKEXT
CKINV
AIN
AIN
AIN
Function
Analog Input for RED Channel
Analog Input for GREEN Channel
Analog Input for BLUE Channel
High impedance inputs that accepts the RED, GREEN, and BLUE channel graphics signals, respectively. The
three channels are identical, and can be used for any colors, but colors are assigned for convenient reference. They
accommodate input signals ranging from 0.5 V to 1.0 V full scale. Signals should be ac-coupled to these pins to
support clamp operation.
Horizontal Sync Input
This input receives a logic signal that establishes the horizontal timing reference and provides the frequency refer-
ence for pixel clock generation. The logic sense of this pin is controlled by HSPOL. Only the leading edge of
HSYNC is active. When HSPOL = 0, the falling edge of HSYNC is used. When HSPOL = 1, the rising edge is
active. The input includes a Schmitt trigger for noise immunity, with a nominal input threshold of 1.5 V.
Electrostatic Discharge (ESD) protection diodes will conduct heavily if this pin is driven more than 0.5 V above
the 3.3 V power supply (or more than 0.5 V below ground). If a 5 V signal source is driving this pin, the signal
should be clamped or current limited.
Clock Generator Coast Input (optional)
This input may be used to cause the pixel clock generator to stop synchronizing with HSYNC and continue pro-
ducing a clock at its present frequency and phase. This is useful when processing sources that fail to produce hori-
zontal sync pulses when in the vertical interval. The COAST signal is generally NOT required for PC-generated
signals. The logic sense of this pin is controlled by CSTPOL. COAST may be asserted at any time. When not
used, this pin must be grounded and CSTPOL programmed to 1. CSTPOL defaults to 1 at power-up.
External Clamp Input (optional)
This logic input may be used to define the time during which the input signal is clamped to ground, establishing a
black reference. It should be exercised when a black signal is known to be present on the analog input channels,
typically during the back porch period of the graphics signal. The CLAMP pin is enabled by setting control bit
EXTCLMP to 1 (default power-up is 0). When disabled, this pin is ignored and the clamp timing is determined
internally by counting a delay and duration from the trailing edge of the HSYNC input. The logic sense of this pin
is controlled by CLAMPOL. When not used, this pin must be grounded and EXTCLMP programmed to 0.
Sync On Green Slicer Input (optional)
This input is provided to assist in processing signals with embedded sync, typically on the GREEN channel. The
pin is connected to a high speed comparator with an internally-generated threshold of 0.15 V. When connected to
a dc-coupled graphics signal with embedded sync, it will produce a noninverting digital output on SOGOUT that
changes state whenever the input signal crosses 0.15 V. This is usually a composite sync signal, containing both
vertical and horizontal sync information that must be separated before passing the horizontal sync signal to HSYNC.
The SOG slicer comparator continues to operate when the AD9884A is put into a power-down state. When not
used, this input should be grounded.
External Clock Input (optional)
This pin may be used to provide an external clock to the AD9884A, in place of the clock internally-generated from
HSYNC. This input is enabled by programming EXTCLK to 1. When an external clock is used, all other internal
functions operate normally. When unused, this pin should be tied through a 10 kΩ resistor to GROUND, and
EXTCLK programmed to 0. The clock phase adjustment still operates when an external clock source is used.
Sampling Clock Inversion (optional)
This pin may be used to invert the pixel sampling clock, which has the effect of shifting the sampling phase
180 degrees. This is in support of Alternate Pixel Sampling mode, wherein higher frequency input signals (up to
280 Mpps) may be captured by first sampling the odd pixels, then capturing the even pixels on the subsequent
frame. This pin should be exercised only during blanking intervals (typically vertical blanking) as it may produce
several samples of corrupted data during the phase shift. CKINV should be grounded when not used.
PIN FUNCTION DESCRIPTIONS
–6–
REV. C