ISL33002IUZ Intersil, ISL33002IUZ Datasheet
ISL33002IUZ
Specifications of ISL33002IUZ
Related parts for ISL33002IUZ
ISL33002IUZ Summary of contents
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... DEVICE B GND CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners Compatible Bi-Directional Buffer (see page 15 BUS WITH 2.7kΩ PULL-UP RESISTOR ...
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... PART (Notes MARKING ISL33001IRTZ 3001 ISL33001IRT2Z 01R2 ISL33001IBZ 33001 IBZ ISL33001IUZ 33001 ISL33002IRTZ 3002 ISL33002IRT2Z 02R2 ISL33002IUZ 33002 ISL33003IRTZ 3003 ISL33003IRT2Z 03R2 ISL33003IUZ 33003 ISL33001MSOPEVAL1Z ISL33001 Evaluation Board ISL33002MSOPEVAL1Z ISL33002 Evaluation Board ISL33003MSOPEVAL1Z ISL33003 Evaluation Board NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations) ...
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Pin Configurations ISL33002 (8 LD TDFN) TOP VIEW V 1 CC2 SCL_OUT 2 PAD SCL_IN 3 GND 4 ISL33003 (8 LD TDFN) TOP VIEW V 1 CC2 SCL_OUT 2 PAD SCL_IN 3 GND 4 Pin Descriptions NAME NOTES V CC1 ...
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Absolute Maximum Ratings (All voltages referenced to GND .-0.3V to +7V CC1 ...
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Electrical Specifications V Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) PARAMETER SYMBOL Enable Delay, On-Off t EN-HL Enable Delay, Off-On t EN-LH Bus Idle Time t IDLE Ready Pin OFF State I OFF Leakage Current ...
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Electrical Specifications V Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) PARAMETER SYMBOL TIMING CHARACTERISTICS SCL/SDA Propagation t PHL Delay High to Low SCL/SDA Propagation t PLH Delay Low to High NOTES: 8. The algebraic convention, ...
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Test Circuits and Waveforms - SDA and SCL pins connected Enable Delay Time Measured on ISL33001 only - ISL33003 performance inferred from ISL33001 ...
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Test Circuits and Waveforms +3.3V 2.7kΩ V CC1 SCL_OUT 2.7kΩ SCL_IN GND V IN 100pF 100pF 100pF FIGURE 5A. TEST CIRCUIT I = CΔV/Δt ACC V CC1 2.7kΩ 100kΩ V CC1 SCL_OUT SCL_IN GND 2nF FIGURE 6. ACCELERATOR CURRENT TEST ...
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SDA_IN M1 V CC1 EN ISL33001 and ISL33003 SCL_IN M3 Application Information The ISL33001, ISL33002, ISL33003 ICs are 2-Wire Bidirectional Bus Buffers designed to drive heavy capacitive loads in open-drain/open-collector systems. The ISL33001, ISL33002, ISL33003 incorporate rise time accelerator circuitry ...
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Coming out of UVLO but prior to a valid connection state, the SDA and SCL pins are pre-charged allow hot insertion. Because the bus at any time can be between 0V and V , pre-charging the I/O ...
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V and provide capacitance buffering. Propagation Delays On a low to high transition, the rising edge signal is determined by the bus pull-up resistor, load capacitance, and the accelerator current from the ISL33001, ISL33002, ...
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Typical Performance Curves 2 5.5V 2.3 CC2 2.2 2 +85°C 2 +25°C 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 2.0 2.5 3.0 3.5 4.0 V (V) CC1 FIGURE 11. I ENABLED CURRENT vs ...
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Typical Performance Curves 100 (mA) OL FIGURE 17. INPUT TO ...
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Typical Performance Curves FIGURE 23. SDA/SCL PIN CAPACITANCE vs TEMPERATURE vs V Die Characteristics SUBSTRATE AND TDFN THERMAL PAD POTENTIAL (POWERED UP): GND PROCESS: 0.25µm CMOS 14 ISL33001, ISL33002, ISL33003 10pF OUT Specified. (Continued) ...
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... Initial Release. Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions ...
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Package Outline Drawing L8.3x3H 8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE (TDFN) Rev 0, 2/08 3.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( 2. . ...
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Package Outline Drawing L8.3x3A 8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 2/10 3.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW 2X 1.950 PIN #1 1 INDEX AREA 0.30 ± 0.10 2.30 ±0.10 ...
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Package Outline Drawing M8.118 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 3, 3/10 3.0±0. PIN TOP VIEW H 0.25 - 0.036 0. A-B D SIDE VIEW 1 (5.80) (4.40) (3.00) ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries ...