NCP1082DEG ON Semiconductor, NCP1082DEG Datasheet - Page 5

• Manufacturer Part Number: NCP1082DEG
• Description: IC CONV CTLR POE-PD 13W 20-TSSOP
• Manufacturer: ON Semiconductor
• Type: Power over Ethernet Switch (PoE)r

Specifications of NCP1082DEG

• Applications: Remote Peripherals (Industrial Controls, Cameras, Data Access)
• Internal Switch(s): Yes
• Current Limit: 500mA
• Voltage - Supply: 0 V ~ 57 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP Exposed Pad, 20-eTSSOP, 20-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 1. Pin Descriptions
VPORTP
VPORTN1
VPORTN2
RTN
ARTN
VDDH
VDDL
CLASS
INRUSH
ILIM1
UVLO
GATE
OSC
NC
COMP
FB
CS
SS
AUX
TEST
EP
Name
Pin No.
6,8
14
16
17
15
13
18
19
12
20
10
11
1
7
2
4
5
3
9
Ground
Ground
Ground
Supply
Supply
Supply
Output
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Positive input power. Voltage with respect to VPORTN
Negative input power. Connected to the source of the internal pass−switch.
DC−DC controller power return. Connected to the drain of the internal pass−switch. It must
be connected to ARTN. This pin is also the drain of the internal pass−switch.
DC−DC controller ground pin. Must be connected to RTN as a single point ground connection
for improved noise immunity.
Output of the 9 V LDO internal regulator. Voltage with respect to ARTN. Supplies the internal
gate driver. VDDH must be bypassed to ARTN with a 1 mF or 2.2 mF ceramic capacitor with
low ESR.
Output of the 3.3 V LDO internal regulator. Voltage with respect to ARTN. This pin can be
used to bias an external low−power LED (1 mA max.) connected to ARTN, and can also be
used to add extra biasing current in the external opto−coupler. VDDL must be bypassed to
ARTN with a 330 nF or 470 nF ceramic capacitor with low ESR.
Classification current programming pin. Connect a resistor between CLASS and VPORTN
Inrush current limit programming pin. Connect a resistor between INRUSH and VPORTN
Operational current limit programming pin. Connect a resistor between ILIM1 and
VPORTN
DC−DC controller under−voltage lockout input. Voltage with respect to VPORTN
a resistor−divider from VPORTP to UVLO to VPORTN
DC−DC controller gate driver output pin.
Internal oscillator frequency programming pin. Connect a resistor between OSC and ARTN.
No connect pin, must not be connected.
Output of the internal error amplifier of the DC−DC controller. COMP is pulled−up internally to
VDDL with a 5 kW resistor. In isolated applications, COMP is connected to the collector of the
opto−coupler. Voltage with respect to ARTN.
DC−DC controller inverting input of the internal error amplifier. In isolated applications, the pin
should be strapped to ARTN to disable the internal error amplifier.
Current−sense input for the DC−DC controller. Voltage with respect to ARTN.
Soft−start input for the DC−DC controller. A capacitor between SS and ARTN determines the
soft−start timing.
When the pin is pulled up, the IEEE detection mode is disabled and the device can be sup-
plied by an auxiliary supply. Voltage with respect to VPORTN
ary supply through a resistor divider.
Digital test pin must always be connected to VPORTN
Exposed pad. Connected to VPORTN
1,2
.
http://onsemi.com
5
1,2
Description
ground.
1,2
1,2
1,2
.
to set an external UVLO threshold.
1,2
. Connect the pin to the auxili-
1,2
. Connect
1,2
1,2
.
.