MAX6974ATL+ Maxim Integrated Products, MAX6974ATL+ Datasheet - Page 17

• Manufacturer Part Number: MAX6974ATL+
• Description: IC LED DRIVER LINEAR 40-TQFN
• Manufacturer: Maxim Integrated Products
• Type: Linear (Serial Interface)r

Specifications of MAX6974ATL+

• Topology: PWM
• Number Of Outputs: 24
• Internal Driver: Yes
• Type - Primary: General Purpose
• Type - Secondary: RGB
• Frequency: 33MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Voltage - Output: 7V
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Operating Temperature: -40°C ~ 125°C
• Current - Output / Channel: 30mA
• Internal Switch(s): Yes
• Low Level Output Current: 6 mA
• High Level Output Current: 30 mA
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Supply Current: 77 mA
• Maximum Power Dissipation: 2963 mW
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Efficiency: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

segments transfer to all cascaded devices, while the
data section reduces in bit length as data transfers
through the cascaded devices. When LOADI is low, the
MAX6974/MAX6975 continuously monitor DIN for
reception of the SYNC pattern (see the Header
Segment section).
The 24-bit header segment consists of an 8-bit fixed
synchronization pattern (SYNC), a 6-bit command pat-
tern (CMD), and a 10-bit counter (CNTR) segment (see
Table 7). LOADI must change from low to high within
plus or minus one clock cycle of the first command bit.
When the SYNC bit pattern 0xE8 is recognized, LOADI
is monitored for the rising edge, allowing the device to
internally synchronize LOADI to CLKI. The six command
bits, CMD[5:0], consist of bits C1 and C0 repeated
three times. The four commands used by the MAX6974/
MAX6975 are defined by the two bits, C1 and C0.
The counter segment is incremented by one for each
cascaded device with an internal fault detected. Use the
counter segment to collect fault data across the cas-
caded chain.
HDR[23:0]
Complete 24-bit header segment.
SYNC[7:0]
Synchronization bit pattern 0xE8 is recognized by the
MAX6974/MAX6975 during intervals when LOADI is low.
The SYNC bit pattern, followed by the rising edge of
Table 7. Serial-Interface Header
Figure 7. Header-Segment Timing
23
7
1
22
6
1
21
5
1
20
4
0
SYNC
LOADI
(CONTINUOUS)
DIN
CLKI
______________________________________________________________________________________
19
3
1
18
2
0
1
0
1
17
1 1
1
0
SYNC
16
0
0
0
Header Segment
1
C1
0 0
15
1
C0
0
14
0
C1 C0 C1 C0 C1 C0
24-Output PWM LED Drivers
C1
13
COMMAND
1
CMD
HEADER
C0
12
0
HDR
C1
11
1
LOADI, internally synchronizes the timing relationship
between CLKI and DIN with the LOADI signal. The
synchronization pattern must be 0xE8.
CMD[5:0]
Send command bits C1 and C0 three times in succes-
sion. The command bits define how many data bits are
received and where the data is loaded. The four com-
mands are:
CNTR[9:0]
This is the counter for open LED or overtemperature fault
conditions. The host sends the header segment with the
counter value set to zero. The counter value is incre-
mented one count by each device that detects a fault
condition in the cascaded chain. The accumulated count
value returns to the host from the last device in the cas-
cade chain. The command determines which fault type
is incremented to the counter (see LED Open-Circuit and
Overtemperature Detection Counter section):
CMD[1:0] = X0
CMD[1:0] = X1
b9 b8 b7 b6 b5 b4 b3 b2
C0
10
C1:C0
0
00
01
10
11
for Message Boards
b9
9
9
COUNTER
b8
8
8
Load individual PWM
Load CALDAC
Load global-intensity PDM
Load configuration
b7
7
7
b1 b0
Overtemperature faults counted
Open LED faults counted
COMMAND
b6
6
6
DATA
b5
5
5
CNTR
b4
4
4
b3
3
3
b2
2
2
CMD[5:0]
000000
010101
101010
111111
b1
1
1
b0
0
0
17