LT1186FIS Linear Technology, LT1186FIS Datasheet - Page 13

• Manufacturer Part Number: LT1186FIS
• Description: IC SWTCH REG CCFL DAC PROG16SOIC
• Manufacturer: Linear Technology
• Series: Bits-to-Nits™r
• Type: CCFL Controllerr

Specifications of LT1186FIS

• Frequency: 175 ~ 225 kHz
• Current - Supply: 6mA
• Voltage - Supply: 3 V ~ 6.5 V
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Output: -

APPLICATIONS
2-Wire Interface (Pulse Mode)
In increment/decrement pulse mode, a logic high at UP/
DN programs the counter into increment mode and each
rising edge of CLK increments the upper six bits of the
counter by one. The counter stops incrementing at
11111100B. A logic low at UP/DN programs the counter
into decrement mode and each rising edge of CLK decre-
ments the upper six bits of the counter by one. The counter
stops decrementing at 00000000B. The last two LSBs are
always zero in this mode. I
(50 A)/255. The upper 6-bit counter = B
B
decrement mode, tie CS to V
once on power-up.
Simplified Lamp Current Programming
A programming block in the LT1186F controls lamp
current, permitting either grounded lamp or floating lamp
configurations. Grounded configurations control lamp
current by directly controlling one-half of actual lamp
current and converting it to a feedback signal to close a
control loop. Floating configurations control lamp current
by directly controlling the Royer’s primary-side converter
current and generating a feedback signal to close a control
loop.
Previous backlighting solutions have used a traditional
error amplifier in the control loop to regulate lamp current.
This approach converted an RMS current into a DC voltage
for the input of the error amplifier. This approach used
several time constants in order to provide stable loop
D
CLK
OUT
D
1
CS
IN
= B
Hi-Z
0
= 0. To configure the LT1186F into increment/
t
CSS
t
CKS
t
D7
DV
D7
U
INFORMATION
D6
U
D6
OUT
CC
and pulse the UP/DN pin
= (B
W
D5
7
t
B
D5
DS
7
Figure 2. SPI Interface Timing Specification
6
B
B
6
5
B
B
5
4
B
B
D4
U
4
3
B
B
3
D4
2
B
B
2
1
t
DH
and
B
0
)
D3
D3
frequency compensation. This compensation scheme
meant that the loop had to be fairly slow and that output
overshoot with start-up or overload conditions had to be
carefully evaluated in terms of transformer stress and
breakdown voltage requirements.
The LT1186F eliminates the error amplifier concept en-
tirely and replaces it with a lamp current programming
block. This block provides an easy-to-use interface to
program lamp current. The programmer circuit also re-
duces the number of time constants in the control loop by
combining the error signal conversion scheme and fre-
quency compensation into a single capacitor. The control
loop thus exhibits the response of a single pole system,
allows for faster loop transient response and virtually
eliminates overshoot under start-up or overload condi-
tions.
Lamp current is programmed at the input of the program-
mer block, the I
regulator and accepts a DC input current signal of 0 A to
50 A from the DAC. This input signal is converted to a 0 A
to 250 A source current at the CCFL V
mer circuit is simply a current-to-current converter with a
gain of five. The typical input current programming range
for 0mA to 6mA lamp current is 0 A to 50 A.
The I
oscillate with capacitance greater than 10pF. For example,
loading the I
oscillation and erratic CCFL regulator operation because
of the probe’s respective input capacitance. A current
meter in series with the I
t
CSLO
t
DO
CCFL
D2
D2
pin is sensitive to capacitive loading and will
CCFL
t
CKHI
CCFL
pin with a 1 or 10 scope probe causes
D1
D1
t
pin. This pin is the input of a shunt
CKLO
CCFL
D0
pin will also produce oscil-
D0
C
pin. The program-
t
CKH
t
CSH
D7
LT1186F
t
DZ
t
CSHI
13
LT1186F • F02
Hi-Z