IR2166STRPBF International Rectifier, IR2166STRPBF Datasheet - Page 24

• Manufacturer Part Number: IR2166STRPBF
• Description: IC PFC BALLAST CTLR 16-SOIC
• Manufacturer: International Rectifier
• Type: PFC/Ballast Controllerr

Specifications of IR2166STRPBF

• Frequency: 39 ~ 50 kHz
• Current - Supply: 10mA
• Current - Output: 400mA
• Voltage - Supply: 11.5 V ~ 15.6 V
• Operating Temperature: -25°C ~ 125°C
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The VBUS pin is regulated against a fixed
internal 4V reference voltage for regulating the
DC bus voltage (Figure 9). The feedback loop
is performed by an operational transconductance
amplifier (OTA) that sinks or sources a current
to the external capacitor at the COMP pin. The
resulting voltage on the COMP pin sets the
threshold for the charging of the internal timing
capacitor (C1) and therefore programs the on-
time of MPFC. During preheat and ignition
modes of the ballast section, the gain of the
OTA is set to a high level to raise the DC bus
level quickly. When the voltage on the V
exceeds 3V, the gain is set to a low level to
reduce overshoot. When the voltage on the V
pin exceeds 4V, the gain is set to a high level
again to minimize the transient on the DC bus
which can occur during ignition. During run
mode, the gain is then decreased to a lower
level necessary for achieving high power factor
and low THD.
IR2166 & (PbF)
24
(+)
(-)
RVBUS1
RVBUS
Figure 8:IR2166 simplified PFC control circuit
DCOMP
COMP
VBUS
CCOMP
Control
PFC
LPFC
COM
PFC
ZX
RZX
RPFC
MPFC
DFPC
BUS
CBUS
BUS
pin
The off-time of MPFC is determined by the time
it takes the LPFC current to discharge to zero.
This zero current level is detected by a
secondary winding on LPFC which is connected
to the ZX pin. A positive-going edge exceeding
the internal 2V threshold signals the beginning
of the off-time. A negative-going edge on the
ZX pin falling below 1.7V will occur when the
LPFC current discharges to zero which signals
the end of the off-time and MPFC is turned on
again (Figure 10). The cycle repeats itself
indefinitely until the PFC section is disabled due
to a fault detected by the ballast section (Fault
Mode), an over-voltage or under-voltage
condition on the DC bus, or, the negative
transition of ZX pin voltage does not occur.
Should the negative edge on the ZX pin not occur,
MPFC will remain off until the watch-dog timer
forces a turn-on of MPFC for an on-time duration
programmed by the voltage on the COMP pin.
The watch-dog pulses occur every 400 s
indefinitely until a correct positive- and negative-
going signal is detected on the ZX pin and normal
PFC operation is resumed.
COMP
VBUS
ZX
1
6
7
3.0V
Figure 9: IR2166 detailed PFC control circuit
7.6V
COMP2
4.0V
Run Mode Signal
GAIN
Discharge
2.0V
VCC to
UVLO-
OTA1
COMP3
M1
4.3V
C1
COMP5
Fault Mode Signal
COMP4
M2
R1
R2 Q
S
RS4
Q
S
R
RS3
Q
Q
WATCH
TIMER
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DOG
VCC
8
PFC