LT1166CS8 Linear Technology, LT1166CS8 Datasheet - Page 4

• Manufacturer Part Number: LT1166CS8
• Description: IC BIAS SYS AUTO PWR-OUTPT 8SOIC
• Manufacturer: Linear Technology

Specifications of LT1166CS8

• Configuration: High and Low Side, Synchronous
• Input Type: Non-Inverting
• Number Of Configurations: 1
• Number Of Outputs: 2
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Voltage - Supply: -
• Delay Time: -
• Current - Peak: -
• High Side Voltage - Max (bootstrap): -

LT1166
TYPICAL PERFORMANCE CHARACTERISTICS
PIN
V
for the output transistors. Operating supply current enters
Pin 1 and a portion biases internal circuitry; Pin 1 current
should be greater than 4mA. Pin 1 voltage is internally
clamped to 12V with respect to V
should be limited to 75mA maximum.
V
drives V
the input impedance drops to 200 and the input current
must be limited to 5mA or V
V
control loop that maintains the output voltage at the input
voltage.
V
voltage for the output transistors. Operating supply cur-
rent exits this pin; Pin 4 current should be greater than
4mA. Pin 4 voltage is internally clamped to – 12V with
respect to V
75mA maximum.
4
TOP
IN
OUT
BOTTOM
6V.
–0.080
–0.090
–0.100
–0.110
–0.120
0.120
0.110
0.100
0.090
0.080
U
(Pin 2): Pin 2 is the input to a unity gain buffer which
(Pin 1): Pin 1 establishes the top side drive voltage
(Pin 3): Pin 3 of the LT1166 is the output of a voltage
0
FUNCTIONS
Input Transconductance vs
Supply Voltage
OUT
25 C
(Pin 4): Pin 4 establishes the bottom side drive
1
U
(Pin 3). During a fault condition (short circuit)
OUT
– 55 C
2
125 C
SUPPLY VOLTAGE (V)
3
and the pin current should be limited to
4
– 55 C
25 C
U
5
V
R
R
IN
6
L
IN
125 C
= 0
= 200mV
= 0
W
7
IN
to V
8
gm
gm
LT1166 • TPC10
CC
EE
U
OUT
9
OUT
10
and the pin current
limited to less than
0.01
0.1
10
1
0.01
Total Harmonic Distortion vs
Frequency
R
P
SEE FIGURE 8
O
L
= 10
= 1W
0.1
FREQUENCY (kHz)
SENSE
by the current control loop and it controls the output
quiescent current in the bottom side power device. Limit
the maximum differential voltage between Pin 5 and Pin 3
to 6V during fault conditions.
I
voltage at V
tion. The maximum reverse voltage on Pin 6 with respect
to V
I
voltage at V
The maximum reverse voltage on Pin 7 with respect to
V
SENSE
the current control loop and it controls the output quies-
cent current in the top side power device. Limit the
maximum differential voltage between Pin 8 and Pin 3 to
1
LIM
LIM
OUT
6V during fault conditions.
OUT
–
+
is – 6V.
(Pin 6): The negative side current limit, limits the
(Pin 7): The positive side current limit, limits the
–
+
10
is 6V.
(Pin 8): The Sense
(Pin 5): The Sense
LT1166 • TPC11
BOTTOM
TOP
100
to V
to V
OUT
1000
OUT
100
during a positive fault condition.
10
1
10
Sense Pin Voltage Referenced to
V
+
during a negative fault condi-
OUT
R
–
pin voltage is established by
SENSE
8
pin voltage is established
vs Load Current
SINKING
6
= 100
LOAD CURRENT (mA)
4
V
BOTTOM
2
0
2
SOURCING
4
V
TOP
6
LT1166 • TPC12
8
10