MAX5048BAUT+T Maxim Integrated Products, MAX5048BAUT+T Datasheet - Page 7

• Manufacturer Part Number: MAX5048BAUT+T
• Description: IC MOSFET DVR HIGH SPEED SOT23-6
• Manufacturer: Maxim Integrated Products
• Type: Low Sider

Specifications of MAX5048BAUT+T

• Configuration: Low-Side
• Input Type: Inverting and Non-Inverting
• Delay Time: 12ns
• Current - Peak: 7.6A
• Number Of Configurations: 1
• Number Of Outputs: 1
• Voltage - Supply: 4 V ~ 12.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: *
• Rise Time: 82 ns
• Fall Time: 12.5 ns
• Supply Voltage (min): 4 V
• Supply Current: 1.5 mA
• Maximum Power Dissipation: 727 mW
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Drivers: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• High Side Voltage - Max (bootstrap): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 1. Timing Diagram and Test Circuit
The quiescent current is 0.95mA typical. The current
required to charge and discharge the internal nodes is
frequency dependent (see the Typical Operating
Characteristics). The MAX5048A/MAX5048B power dis-
sipation when driving a ground referenced resistive
load is:
where D is the fraction of the period the MAX5048A/
MAX5048Bs’ output pulls high, R
mum on-resistance of the device with the output high
(P-channel), and I
MAX5048A/MAX5048B.
For capacitive loads, the power dissipation is:
where C
voltage, and FREQ is the switching frequency.
The MOSFET drivers MAX5048A/MAX5048B source-
and-sink large currents to create very fast rise and fall
edges at the gate of the switching MOSFET. The high
di/dt can cause unacceptable ringing if the trace
lengths and impedances are not well controlled. The
LOAD
P = D x R
P = C
is the capacitive load, V+ is the supply
7.6A, 12ns, SOT23/TDFN, MOSFET Driver
LOAD
_______________________________________________________________________________________
LOAD
P_OUT AND
TOGETHER
N_OUT
ON(MAX)
IN+
is the output load current of the
TIED
x (V+)
V
IL
Layout Information
2
x I
ON (MAX)
x FREQ
LOAD 2
t
D–OFF
INPUT
90%
10%
is the maxi-
V+
t
F
V+
IN+
IN-
TIMING DIAGRAM
TEST CIRCUIT
MAX5048A
MAX5048B
GND
following PC board layout guidelines are recommended
when designing with the MAX5048A/MAX5048B:
• Place one or more 0.1µF decoupling ceramic capaci-
• There are two AC current loops formed between the
N_OUT
P_OUT
tor(s) from V+ to GND as close to the device as possi-
ble. At least one storage capacitor of 10µF (min)
should be located on the PC board with a low resis-
tance path to the V+ pin of the MAX5048A/MAX5048B.
device and the gate of the MOSFET being driven.
The MOSFET looks like a large capacitance from
gate to source when the gate is being pulled low.
The active current loop is from N_OUT of the
MAX5048A/MAX5048B to the MOSFET gate to the
MOSFET source and to GND of the MAX5048A/
MAX5048B. When the gate of the MOSFET is being
pulled high, the active current loop is from P_OUT of
the MAX5048A/MAX5048B to the MOSFET gate to
the MOSFET source to the GND terminal of the
decoupling capacitor to the V+ terminal of the
decoupling capacitor and to the V+ terminal of the
MAX5048A/MAX5048B. While the charging current
loop is important, the discharging current loop is crit-
ical. It is important to minimize the physical distance
and the impedance in these AC current paths.
V
IH
C
L
t
D–ON
OUTPUT
t
R
7