A3946KLP Allegro Microsystems Inc, A3946KLP Datasheet - Page 8

• Manufacturer Part Number: A3946KLP
• Description: IC CTRLR MOSFET 16-TSSOP
• Manufacturer: Allegro Microsystems Inc

Specifications of A3946KLP

• Applications: DC Motor Controller, Brushless (BLDC), 3 Phase
• Number Of Outputs: 1
• Voltage - Supply: 7 V ~ 60 V
• Operating Temperature: -40°C ~ 135°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP Exposed Pad, 16-eTSSOP, 16-HTSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Output: -
• Voltage - Load: -

A3946
Bootstrap Capacitor Selection. C
rectly selected to ensure proper operation of the device. If
too large, time is wasted charging the capacitor, with the
result being a limit on the maximum duty cycle and PWM
frequency. If the capacitor is too small, the voltage drop can
be too large at the time the charge is trans ferred from the
C
To keep the voltage drop small:
where a factor in the range of 10 to 20 is reasonable. Using
20 as the factor:
and
The voltage drop on the BOOT pin, as the MOSFET is being
turned on, can be approximated by:
For example, given a gate charge, Q
typical BOOT pin voltage of 12 V, the value of the Boot
capacitor, C
Therefore, a 0.22 μF ceramic (X7R) capacitor can be chosen
for the Boot capacitor.
In that case, the voltage drop on the BOOT pin, when the
high-side MOSFET is turned on, is:
Bootstrap Charging. It is good practice to ensure that the
high-side bootstrap capacitor is completely charged before a
high-side PWM cycle is re quest ed.
The time required to charge the capacitor can be ap prox i-
mat ed by:
BOOT
to the MOSFET gate.
BOOT
C
Delta_v = Q
BOOT
Delta_v = 160 nC / 0.22 μF = 0.73 V
Q
t
C
CHARGE
, can be determined by:
BOOT
BOOT
= (160 nC
= C
= Q
= C
Q
BOOT
GATE
GATE
BOOT
BOOT
×
×
×
/ C
(Delta_v / 100 mA)
>> Q
20) / 12 V ≈ 0.266 μF
V
20 / V
BOOT
BOOT
GATE
BOOT
= Q
GATE
BOOT
GATE
, of 160 nC, and the
Application Information
must be cor-
×
20
Half-Bridge Power MOSFET Controller
At power-up and when the drivers have been disabled for
a long time, the bootstrap capacitor can be completely
discharged. In this case, Delta_v can be considered to be the
full high-side drive voltage, 12 V. Otherwise, Delta_v is the
amount of voltage dropped during the charge transfer, which
should be 400 mV or less. The capacitor is charged whenever
the S pin is pulled low, via a GL PWM cycle, and current
fl ows from VREG through the internal bootstrap diode
circuit to C
Power Dissipation. For high ambient temperature
applications, there may be little margin for on-chip power
con sump tion. Careful attention should be paid to ensure that
the op er at ing conditions allow the A3946 to remain in a safe
range of junction temperature.
The power consumed by the A3946 can be es ti mat ed as:
where:
and
in either case, where
and
where
Pd_cpump = (2V
Pd_cpump = (V
Pd_switching_loss = Q
Pd_bias = V
Ratio = 10 Ω / (R
P_total = Pd_bias + Pd_cpump + Pd_switching_loss
I
AVE
BOOT
= Q
.
BB
GATE
BB
BB
×
– V
– V
I
×
VBB
REG
2
REG
GATE
GATE
, typically 3 mA,
×
) I
) I
f
+ 10 Ω).
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
AVE
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
PWM
×
AVE
, for V
V
, for V
REG
×
BB
BB
2
> 15 V,
< 15 V, or
×
f
PWM
Ratio,
8