A3949SLP Allegro Microsystems Inc, A3949SLP Datasheet - Page 5

• Manufacturer Part Number: A3949SLP
• Description: IC MOTOR DRVR PWM FULL 16TSSOP
• Manufacturer: Allegro Microsystems Inc

Specifications of A3949SLP

• Applications: PWM Motor Driver
• Number Of Outputs: 1
• Current - Output: ±2.8A
• Voltage - Supply: 8 V ~ 36 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP Exposed Pad, 16-eTSSOP, 16-HTSSOP
• Operating Current: 8.5mA
• Operating Temperature Classification: Commercial
• Package Type: TSSOP EP
• Operating Supply Voltage (max): 36V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Voltage - Load: -
• Lead Free Status / Rohs Status: Compliant

A3949
VREG. This supply voltage is used to operate the sink-
side DMOS outputs. VREG is internally monitored and in
the case of a fault condition, the outputs of the device are
disabled. The VREG pin should be decoupled with a 0.22 F
capacitor to ground.
Charge Pump. The charge pump is used to generate a
supply above VBB to drive the source-side DMOS gates. A
0.1 uF ceramic monolithic capacitor should be connected
between CP1 and CP2 for pumping purposes. A 0.1 uF
ceramic monolithic capacitor should be connected between
VCP and VBB to act as a reservoir to run the high side
DMOS devices. The VCP voltage is internally monitored,
and in the case of a fault condition, the outputs of the device
are disabled.
Shutdown. In the event of a fault due to excessive junction
temperature, or low voltage on VCP or VREG, the outputs of
the device are disabled until the fault condition is removed.
At power-up, the UVLO circuit disables the drivers.
Control Logic Table
* To prevent reversal of current during fast decay SR (synchronous rectifi cation), the outputs
go to the high impedance state as the current approaches zero.
PHASE ENABLE MODE
X
X
1
0
1
0
1
1
0
0
0
X
X
X
1
0
0
X
SLEEP
Functional Description
1
1
1
1
1
0
OUTA
Hi-Z
H
H
L
L
L
DMOS Full-Bridge Motor Driver
OUTB
Sleep Mode. Control input SLEEP is used to minimize
power consumption when the A3949 is not in use. This
disables much of the internal circuitry, including the low-side
gate supply and the charge pump. A logic low on this pin
puts the device into Sleep mode. A logic high allows normal
operation. After coming out of Sleep mode, the user should
wait 1 ms before applying PWM signals, to allow the charge
pump to stabilize.
Braking. The braking function is implemented by driv-
ing the device in slow decay mode via the MODE pin, and
applying an enable chop command. Because it is possible to
drive current in both directions through the DMOS switches,
this confi guration effectively shorts out the motor-generated
BEMF, as long as the enable chop mode is asserted on the
ENABLE pin. The maximum current can be approximated
by V
mum ratings of the device are not exceeded in worse case
braking situations of high speed and high inertial loads.
Hi-Z
H
H
L
L
L
BEMF
/ R
L
. Care should be taken to insure that the maxi-
Brake (slow decay)
Fast decay SR*
Fast decay SR*
Sleep mode
Function
Forward
Reverse
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
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