CS7054YDWR16 ON Semiconductor, CS7054YDWR16 Datasheet - Page 7

• Manufacturer Part Number: CS7054YDWR16
• Description: IC CTRLR PWM FET LOW SIDE 16SOIC
• Manufacturer: ON Semiconductor

Specifications of CS7054YDWR16

• Applications: DC Motor Driver
• Number Of Outputs: 1
• Current - Output: 400mA
• Voltage - Supply: 8 V ~ 16 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Voltage - Load: -
• Other names: CS7054YDWR16OSTR

leads are low impedance inputs thereby creating a good
current sensing amplifier. Both leads source 50 A while the
chip is in run mode. R
to minimize error in the I
between 1.0 V and 4.0 V.
I
the MOSFET low for the remainder of the oscillator cycle
(fault mode). At the start of the next cycle, the latch is reset
and the IC reverts back to run mode until another fault
occurs. If a number of faults occur in a given period of time,
the IC “times out” and disables the MOSFET for a long
period of time to let it cool off. This is accomplished by
charging the C
condition occurs. If a cycle goes by with no overcurrent fault
occurring, an even smaller amount of charge will be
removed from C
eventually C
will be set. The fault latch will not be reset until the C
discharges to 0.6 V. This action will continue indefinitely if
the fault persists.
where:
Sleep State
when CTL lead is brought to less than 0.5 V. All functions
are disabled in this mode, except for the regulator.
Inhibit
latch is set and the external MOSFET will be turned off for
the remainder of the oscillator cycle. The latch is then reset
at the start of the next cycle.
LIM
When the current through the external MOSFET exceeds
The off time and on time are set by the following:
This device will enter into a low current mode (< 275 A)
When the inhibit voltage is greater than 2.5 V the internal
, an internal latch is set and the output pulls the gate of
I AVG + (295.5 mA
Off Time + C FLT
On Time + C FLT
I AVG + (300 mA
FLT
FLT
will charge up to 2.4 V and the fault latch
DC + PWM Duty Cycle
FLT
capacitor each time an over current
. If enough faults occur together,
CS
LIM
should be much less than 1000
DC) * [4.5 mA
equation. I
DC) * 4.5 mA
2.4 V * 0.6 V
2.4 V * 0.6 V
4.5 mA
I AVG
ADJ
should be biased
(1 * DC)]
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FLT
CS7054
7
Overvoltage Shutdown
event. This is a real time fault event and does not set the
internal latch and therefore is independent of the oscillator
timing (i.e. asynchronous). There is no undervoltage
lockout. The device will shutdown gracefully once it runs
out of headroom. This happens at the point when VREG falls
out of regulation.
Reverse Battery
Therefore, a series diode is required between the battery and
the V
Load Dump
a 51
current flow into the IC in the event of a 40 V peak transient
condition.
Using the CS7054 as a Frequency Converter
frequency converter. In the setup shown, a 150 Hz square
wave from a microprocessor is converted to a 10 kHz square
wave. The duty cycle of each waveform is identical. The
amplitude of the input waveform is 5.0 V, but does not need
to be. The input amplitude requirement just needs to be high
enough to switch the external bipolar transistor. The 10 kHz
oscillator frequency is setup per the oscillator section of this
data sheet.
6.2 k resistors supplies 5.0 V to the CTL pin when the input
duty cycle is at 100%. This also makes the output waveform
100%.
input waveform. Care must be taken to provide the
appropriate DC level on the control pin in addition to
providing the required response time.
defeated by grounding the I
connecting the I
The IC will disable the output during an overvoltage
The CS7054 will not survive a reverse battery condition.
V
Figure 9 shows the CS7054 configured for use as a
The external resistor divider composed of the 3.6 k and
The RC filter (1.0 M and 0.1 F) sets up a pole at 1.6 Hz:
In this case, the pole is 2 orders of magnitude below the
*Note the current limit feature of the CS7054 has been
CC
CC
f +
resistor, (R
is internally clamped to 30 V. It is recommended that
+ 1.6 Hz
lead.
2pRC
1
ADJ
+
S
) is placed in series with V
2p 1 MW )
lead to V
SENSE+
REG
.
(6.2 k)(3.6 k)
6.2 k)3.6 k
and the I
1
SENSE–
(0.1 mF)
CC
to limit the
pins and