IR3505MPBF International Rectifier, IR3505MPBF Datasheet - Page 7

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IR3505MPBF

Manufacturer Part Number
IR3505MPBF
Description
IC XPHASE3 CONTROL 16-MLPQ
Manufacturer
International Rectifier
Series
XPhase3™r
Datasheet

Specifications of IR3505MPBF

Applications
Processor
Current - Supply
3mA
Voltage - Supply
8 V ~ 16 V
Operating Temperature
0°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
16-MLPQ
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IR3505MPBF
Quantity:
9 000
SYSTEM THEORY OF OPERATION
PWM Control Method
The PWM block diagram of the XPhase
trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is used
for the voltage control loop. Input voltage is sensed in phase ICs and feed-forward control is realized. The PWM
ramp slope will change with the input voltage and automatically compensate for changes in the input voltage. The
input voltage can change due to variations in the silver box output voltage or due to the wire and PCB-trace voltage
drop related to changes in load current.
Frequency and Phase Timing Control
The oscillator is located in the Control IC and the system clock frequency is programmable from 250kHz to 9MHZ
by an external resistor. The control IC system clock signal (CLKOUT) is connected to CLKIN of all the phase ICs.
The phase timing of the phase ICs is controlled by the daisy chain loop, where control IC phase clock output
(PHSOUT) is connected to the phase clock input (PHSIN) of the first phase IC, and PHSOUT of the first phase IC is
connected to PHSIN of the second phase IC, etc. and PHSOUT of the last phase IC is connected back to PHSIN of
the control IC. During power up, the control IC sends out clock signals from both CLKOUT and PHSOUT pins and
detects the feedback at PHSIN pin to determine the phase number and monitor any fault in the daisy chain loop.
Figure 2 shows the phase timing for a four phase converter. The switching frequency is set by the resistor ROSC as
shown in Figure 9. The clock frequency equals the number of phase times the switching frequency.
LDO AMPLIFIER
ERROR
AMPLIFIER
IVSETPT
CONTROL IC
Page 7 of 19
CLOCK GENERATOR
REMOTE SENSE
AMPLIFIER
+
-
IROSC
VDAC
+
-
+
-
VDRP
AMP
VSETPT
VDRP
IIN
PHSOUT
PHSIN
VO
VDAC
LGND
EAOUT
FB
CLKOUT
RVSETPT
RCOMP
CCOMP
CCOMP1
RFB1
CFB
RDRP1
CDRP
GATE DRIVE
VOLTAGE
RFB
RDRP
TM
architecture is shown in Figure 1. Feed-forward voltage mode control with
Figure 1 PWM Block Diagram
PHSOUT
PHSOUT
PHSIN
CLKIN
ISHARE
DACIN
EAIN
ISHARE
DACIN
CLKIN
PHSIN
EAIN
3K
3K
CLK
D
SHARE ADJUST
ERROR AMPLIFIER
CLK
D
SHARE ADJUST
ERROR AMPLIFIER
Q
PWM
COMPARATOR
Q
PWM
COMPARATOR
+
-
+
-
RAMP
DISCHARGE
CLAMP
RAMP
DISCHARGE
CLAMP
ENABLE
ENABLE
1
-
1
VID6
-
VID6
+
VID6
VID6
+
VID6
VID6
-
+
-
+
+
-
+
-
PHASE IC
PHASE IC
2
2
PWM LATCH
PWM LATCH
1
2
BODY
BRAKING
COMPARATOR
1
2
BODY
BRAKING
COMPARATOR
DOMINANT
D
CLK
DOMINANT
RESET
D
CLK
RESET
VID6
VID6
VID6
VID6
Q
Q
Q
Q
+
4
5
+
4
5
+
+
CURRENT
SENSE
AMPLIFIER
CURRENT
SENSE
AMPLIFIER
+
-
+
-
VCC
VCCH
GATEH
SW
VCCL
GATEL
PGND
CSIN+
CSIN-
VCC
VCCH
GATEH
SW
VCCL
GATEL
PGND
CSIN+
CSIN-
Sept 26
CCS
CCS
RCS
RCS
CBST
CBST
th
IR3505
, 2007
COUT
VIN
VOSNS+
VOUT
GND
VOSNS-

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