ISL6566ACRZ Intersil, ISL6566ACRZ Datasheet - Page 10

• Manufacturer Part Number: ISL6566ACRZ
• Description: IC CTRLR PWM 3PHASE BUCK 40-QFN
• Manufacturer: Intersil

Specifications of ISL6566ACRZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 1.5MHz
• Duty Cycle: 66.6%
• Voltage - Supply: 4.75 V ~ 12 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-VFQFN, 40-VFQFPN
• Frequency-max: 1.5MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

V
transitions high. The internal or external MOSFET driver
detects the change in state of the PWM signal and turns off
the synchronous MOSFET and turns on the upper MOSFET.
The PWM signal will remain high until the pulse termination
signal marks the beginning of the next cycle by triggering the
PWM signal low.
Channel-Current Balance
One important benefit of multi-phase operation is the thermal
advantage gained by distributing the dissipated heat over
multiple devices and greater area. By doing this the designer
avoids the complexity of driving parallel MOSFETs and the
expense of using expensive heat sinks and exotic magnetic
materials.
In order to realize the thermal advantage, it is important that
each channel in a multi-phase converter be controlled to
carry about the same amount of current at any load level. To
achieve this, the currents through each channel must be
sampled every switching cycle. The sampled currents, I
from each active channel are summed together and divided
by the number of active channels. The resulting cycle
average current, I
current demand on the converter during each switching
cycle. Channel-current balance is achieved by comparing
the sampled current of each channel to the cycle average
current, and making the proper adjustment to each channel
pulse width based on the error. Intersil’s patented current-
balance method is illustrated in Figure 3, with error
correction for channel 1 represented. In the figure, the cycle
average current, I
sample, I
The filtered error signal modifies the pulse width
commanded by V
I
correction is applied to each active channel.
ER
NOTE: Channel 2 and 3 are optional.
COMP
FIGURE 3. CHANNEL-1 PWM FUNCTION AND CURRENT-
toward zero. The same method for error signal
V
COMP
voltage crosses the sawtooth ramp, the PWM output
1
, to create an error signal I
FILTER
BALANCE ADJUSTMENT
+
I
ER
COMP
AVG
AVG
-
+
f(s)
I
1
, provides a measure of the total load-
, is compared with the channel 1
-
I
AVG
to correct any unbalance and force
SAWTOOTH SIGNAL
10
÷ N
+
-
ER
PWM1
.
Σ
CONTROL
TO GATE
LOGIC
I
I
2
3
n
,
ISL6566A
ISL6566A
Current Sampling
In order to realize proper current-balance, the currents in
each channel must be sampled every switching cycle. This
sampling occurs during the forced off-time, following a PWM
transition low. During this time the current-sense amplifier
uses the ISEN inputs to reproduce a signal proportional to
the inductor current, I
a scaled version of the inductor current. The sample window
opens exactly 1/6 of the switching period, t
PWM transitions low. The sample window then stays open
the rest of the switching cycle until PWM transitions high
again, as illustrated in Figure 4.
The sampled current, at the end of the t
proportional to the inductor current and is held until the next
switching period sample. The sampled current is used only
for channel-current balance.
The ISL6566A supports MOSFET r
to sample each channel’s current for channel-current
balance. The internal circuitry, shown in Figure 5 represents
channel n of an N-channel converter. This circuitry is
repeated for each channel in the converter, but may not be
active depending on the status of the PVCC3 and PVCC2
pins, as described in the PWM Operation section.
FIGURE 4. SAMPLE AND HOLD TIMING
CURRENT
OLD SAMPLE
PWM
L
. This sensed current, I
SWITCHING PERIOD
SAMPLING PERIOD
I
L
TIME
I
DS(ON)
SEN
SAMPLE
SW
current sensing
SEN
, after the
NEW SAMPLE
CURRENT
, is
, is simply
July 27, 2005
FN9200.2