ISL6524ACBZ-T Intersil, ISL6524ACBZ-T Datasheet - Page 9

• Manufacturer Part Number: ISL6524ACBZ-T
• Description: IC CTRLR VRM8.5 PWM TRPL 28-SOIC
• Manufacturer: Intersil

Specifications of ISL6524ACBZ-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 4
• Frequency - Max: 215kHz
• Duty Cycle: 100%
• Voltage - Supply: 10.8 V ~ 13.2 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Frequency-max: 215kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

current increases through the inductor (L
the OC1 comparator trips when the voltage across Q1 (i
r
inhibits outputs 1, 2, and 3, discharges the soft-start capacitor
C
Soft-start capacitor C
ramping up at T2 and initiates a new soft-start cycle. With
OUT2 still overloaded, the inductor current increases to trip
the over-current comparator. Again, this inhibits the outputs,
but the C
4.0V before discharging. Soft-start capacitor C
quickly discharged. The counter increments to 2. The soft-
start cycle repeats at T3 and trips the over-current
comparator. The SS24 pin voltage increases to above 4.0V at
T4 and the counter increments to 3. This sets the fault latch to
disable the converter.
The three linear controllers monitor their respective VSEN
pins for under-voltage. Should excessive currents cause
VSEN3 or VSEN4 to fall below the linear under-voltage
threshold, the respective UV signals set the OC latch or the
FAULT latch, providing respective C
charged. Blanking the UV signals during the C
interval allows the linear outputs to build above the under-
voltage threshold during normal operation. Cycling the bias
input power off then on resets the counter and the fault latch.
An external resistor (R
level for the PWM converter. As shown in Figure 9, the internal
200µA current sink (I
R
enables the over-current comparator (OC). When the voltage
across the upper MOSFET (V
current comparator trips to set the over-current latch. Both
V
DS(ON)
SET
SS24
OCSET
10V
0A
4V
2V
and V
0V
0V
with 28µA current sink, and increments the counter.
) exceeds the level programmed by R
SS24
(V
COUNT
FIGURE 8. OVER-CURRENT OPERATION
SET
DS
= 1
soft-start voltage continues increasing to above
are referenced to V
) that is referenced to V
T0
T1
OCSET
SS13
OCSET
OVERLOAD
REPORTED
COUNT
APPLIED
is quickly discharged. C
FAULT
T2
= 2
) develops a voltage across
) programs the over-current trip
DS(ON)
9
TIME
IN
) exceeds V
SS
and a small capacitor
T3
IN
COUNT
capacitors are fully
. The DRIVE signal
OUT1
T4
= 3
SS
OCSET
). At time T1,
SS13
SET
charge
SS13
is, again,
, the over-
. This
starts
D
•
across R
to MOSFET switching. The over-current function will trip at a
peak inductor current (I
The OC trip point varies with MOSFET’s rDS(ON)
temperature variations. To avoid over-current tripping in the
normal operating load range, determine the ROCSET
resistor value from the equation above with:
For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.
OUT1 Voltage Program
The output voltage of the PWM converter is programmed to
discrete levels between 1.050V and 1.825V. This output
(OUT1) is designed to supply the core voltage of Intel’s
advanced microprocessors. The voltage identification (VID)
pins program an internal voltage reference (DACOUT) with a
TTL-compatible 5-bit digital-to-analog converter (DAC). The
level of DACOUT also sets the PGOOD and OVP thresholds.
Table 1 specifies the DACOUT voltage for the different
combinations of connections on the VID pins. The VID pins
can be left open for a logic 1 input, since they are internally
pulled to the VAUX pin through 5kΩ resistors. Changing the
VID inputs during operation is not recommended and could
toggle the PGOOD signal and exercise the over-voltage
protection. The output voltage program is Intel VRM8.5
compatible.
I
PEAK
1. The maximum r
2. The minimum I
3. Determine I
i
D
where ∆I is the output inductor ripple current.
×
OVER-CURRENT TRIP:
PWM
=
r
DS ON
OC
OCSET
I
--------------------------------------------------- -
OCSET
(
V
FIGURE 9. OVER-CURRENT DETECTION
+
DS
-
r
)
DS ON
>
>
helps V
PEAK
V
CONTROL
×
I
(
OCSET
SET
R
GATE
DS(ON)
OCSET
OCSET
)
for I
PEAK)
I
OCSET
OCSET
DRIVE
200µA
×
OCSET
R
PEAK
at the highest junction temperature
from the specification table
OCSET
determined by:
track the variations of V
VCC
> I
OUT(MAX)
UGATE
PHASE
R
V PHASE
V OCSET
V
OCSET
SET
+
+ (∆I) / 2,
=
=
V
V IN V DS
IN
V IN V SET
i
D
V
+
= +5V
DS
–
April 8, 2005
–
IN
FN9064.1
due