UC2843BD1G ON Semiconductor, UC2843BD1G Datasheet - Page 13

• Manufacturer Part Number: UC2843BD1G
• Description: IC CTRLR CURRENT MODE HP 8-SOIC
• Manufacturer: ON Semiconductor

Specifications of UC2843BD1G

• Pwm Type: Current Mode
• Number Of Outputs: 1
• Frequency - Max: 275kHz
• Duty Cycle: 96%
• Voltage - Supply: 11 V ~ 25 V
• Buck: No
• Boost: Yes
• Flyback: Yes
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: Yes
• Operating Temperature: -25°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Frequency-max: 275kHz
• Duty Cycle (max): 96 %
• Output Voltage: 4.95 V to 5.05 V
• Output Current: 1000 mA
• Mounting Style: SMD/SMT
• Switching Frequency: 500 KHz
• Operating Supply Voltage: 30 V
• Maximum Operating Temperature: + 85 C
• Fall Time: 50 ns
• Minimum Operating Temperature: - 25 C
• Rise Time: 50 ns
• Synchronous Pin: No
• Topology: Boost, Flyback, Forward
• Input Voltage: 15V
• Frequency: 250kHz
• Power Dissipation Pd: 702mW
• Supply Voltage Range: 8.5V To 30V
• Digital Ic Case Style: SOIC
• No. Of Pins: 8
• Operating Temperature Range: -25°C To +85°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

+
-
5.0V Ref
Comp/Latch
R
S
Q
Figure 28. MOSFET Parasitic Oscillations
Figure 30. Isolated MOSFET Drive
Series gate resistor R
caused by the MOSFET input capacitance and any series wiring inductance in
the gate-source circuit.
+
-
5.0V Ref
7(12)
Comp/Latch
+
-
V
CC
7(11)
6(10)
5(8)
3(5)
g
R
S
will damp any high frequency parasitic oscillations
C
Q
Boundary
Isolation
R
R
S
7(12)
+
-
N
V
S
CC
Q1
7(11)
6(10)
5(8)
3(5)
R
g
V
N
+
in
0
-
P
I p k +
50% DC
http://onsemi.com
V (Pin1) * 1.4
Q1
R
V
V
in
S
GS
3 R S
Waveforms
+
0
-
13
N S
N p
25% DC
The MCR101 SCR must be selected for a holding of < 0.5 mA @ T
transistor circuit can be used in place of the SCR as shown. All resistors are 10 k.
+
0
-
The totem pole output can furnish negative base current for enhanced
transistor turn-off, with the addition of capacitor C
MCR
101
I
Figure 29. Bipolar Transistor Drive
B
Figure 31. Latched Shutdown
3905
2N
Base Charge
Removal
3903
8(14)
2N
4(7)
2(3)
1(1)
6(10)
5(8)
3(5)
C1
1
.
EA
R
R
+
Q1
A(min)
Osc
R
V
1.0 mA
in
S
Bias
. The simple two
2R
R
5(9)