FAN1655MTFX Fairchild Semiconductor, FAN1655MTFX Datasheet

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FAN1655MTFX

Manufacturer Part Number
FAN1655MTFX
Description
IC REG LDO DDR BUS 3A 16-ETSSOP
Manufacturer
Fairchild Semiconductor
Datasheet

Specifications of FAN1655MTFX

Applications
Controller, DDR
Voltage - Input
2.3 ~ 3.6 V
Number Of Outputs
1
Voltage - Output
1.1 ~ 1.8 V
Operating Temperature
0°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
16-TSSOP Exposed Pad, 16-eTSSOP, 16-HTSSOP
Polarity
Positive
Input Voltage Max
3.6 V
Output Voltage
1.15 V, 1.25 V, 1.35 V
Output Type
Selectable
Output Current
3 A
Load Regulation
40 mV
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Reference Voltage
1.355 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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©2006 Fairchild Semiconductor Corporation
FAN1655 Rev. 1.1.5
FAN1655
3A DDR Bus Termination Regulator
Description
The
specifically designed for terminating DDR memory bus. It
can both sink and source up to 2.1A continuous, 3A
peak, providing enough current for most DDR appli-
cations. Load regulation meets the JEDEC spec, VTT =
VREFOUT ± 40mV.
The FAN1655 includes a buffered reference voltage
capable of supplying up to 5mA current. On-chip thermal
limiting provides protection against a combination of
power overload and ambient temperature that would
create an excessive junction temperature. A shutdown
input puts the FAN1655 into a low power mode.
The FAN1655 regulator is available in a power-enhanced
eTSSOP™-16, standard SOIC-14, and an 8-Lead MLP
package.
Ordering Information
Block Diagram
Part Number
FAN1655M
FAN1655MX
FAN1655MTF
FAN1655MTFX
FAN1655MPX
FAN1655
VREFOUT
is
VREFIN
a
low-cost
VDDQ
VSSQ
Temperature Range
bi-directional
200k
200k
0°C to 125°C
0°C to 125°C
0°C to 125°C
0°C to 125°C
0°C to 125°C
FAN1655
VDD
+
LDO
VSS
1
VDD
VSS
Features
Applications
Sinks and sources 2.1A continuous, 3A peak
0 to +125°C operating temperature range
5mA Buffered VREFOUT = VDDQ/2
Load regulation: VTT = VREFOUT ± 40mV
On-chip thermal limiting
Low Cost SO-14, Power-Enhanced eTSSOP or
8-pin 5x6mm MLP packages
Low-Current Shutdown Mode
Output Short Circuit Protection
DDR Terminator VTT supply
eTSSOP-16
eTSSOP-16
VDD
VSS
+
Package
SOIC-14
SOIC-14
MLP-8
SHDN
VTTFORCE
VTTFORCE
VTTSENSE
Tape and Reel
Tape and Reel
Tape and Reel
Packing
Rails
Rails
January 2006
www.fairchildsemi.com

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FAN1655MTFX Summary of contents

Page 1

... FAN1655 into a low power mode. The FAN1655 regulator is available in a power-enhanced eTSSOP™-16, standard SOIC-14, and an 8-Lead MLP package. Ordering Information Part Number FAN1655M FAN1655MX FAN1655MTF FAN1655MTFX FAN1655MPX Block Diagram VDDQ VREFOUT VREFIN VSSQ ©2006 Fairchild Semiconductor Corporation FAN1655 Rev. 1.1.5 ...

Page 2

Pin Assignments VDD 1 VDD 2 VTTFORCE 3 VSS 4 FAN1655 VSS 5 VTTFORCE 6 7 VDD 8 VSS 16-Lead Plastic eTSSOP-16 = 4˚C/W* JC *Thermal impedance is measured with the power pad soldered to a 0.5 square inch copper ...

Page 3

Typical Application VDD 100 F 6V GND Typical Performance Characteristics Quiescent Current vs. Temperature 9 7.5 6 4.5 3 1.5 0 - AMBIENT TEMPERATURE (˚C) Figure 2. Quiescent Current vs. Ambient Temperature 1.260 1.255 ...

Page 4

Absolute Maximum Ratings Supply Voltage VDD, VDDQ Junction Temperature Storage Temperature Lead Soldering Temperature, 10 seconds Power Dissipation Recommended Operating Conditions Parameter Supply Voltage VDD Supply Voltage VDDQ Ambient Operating Temperature VREFIN Electrical Characteristics (VDD = ...

Page 5

Applications Information Output Capacitor selection The JEDEC specification for DDR termination requires that VTT stay within ±40mV of VREF, which must track VDDQ/2 within 1%. During the initial load transient, the output capacitor keeps the output within spec. To stay ...

Page 6

Mechanical Dimensions 16-Lead eTSSOP 5.0 ± 0.1 0.10 TYP 16 6.4 3.2 1 PIN #1 IDENT. ALL LEAD TIPS 0.1 C 1.2 MAX -C- 0.65 TYP 1.7 MIN 9 8 BOTTOM VIEW NOTES: A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION ...

Page 7

Mechanical Dimensions 14-Lead SOIC S8.71-8.51; 7. S6.20-5.80 1.27 S1.75-1.35; Notes: 1. This package conforms to JEDEC MS-012, variation AB, ISSUEC dated May, 1990. 2. All dimensions are in millimeters 3. Standard lead finished ...

Page 8

Mechanical Dimensions 5mm x 6mm 8-Lead MLP 0. TOP VIEW 0. 0.10 C 1.0 MAX C 0.08 SIDE VIEW 0.05 0. PIN #1 IDENT. (OPTIONAL 1.27 BOTTOM VIEW FAN1655 Rev. 1.1.5 5.0 ...

Page 9

... TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended exhaustive list of all such trademarks. ® ACEx™ FAST ActiveArray™ FASTr™ Bottomless™ FPS™ Build it Now™ FRFET™ CoolFET™ ...

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