ISL6217CVZ Intersil, ISL6217CVZ Datasheet - Page 11

• Manufacturer Part Number: ISL6217CVZ
• Description: IC CTRLR PWM INTEL PENT 38-TSSOP
• Manufacturer: Intersil

Specifications of ISL6217CVZ

• Applications: Controller, Intel Pentium® IMVP-IV, IMVP+
• Voltage - Input: 5.5 ~ 25 V
• Number Of Outputs: 1
• Operating Temperature: -10°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 38-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -

A logic low signal present on STPCPU# (pin DSEN#), with
a logic low signal on DPRSLPVR (pin DRSEN), signals the
ISL6217 to reduce the CORE output voltage to the Deep
Sleep level, the voltage on the DSV pin.
A logic high on DPRSLPVR, (pin DRSEN) with a logic low
signal on STPCPU# (pin DSEN#), signals the ISL6217
controller to further reduce the CORE output voltage to the
Deeper Sleep level, which is the voltage on the DRSV pin.
Deep Sleep and Deeper Sleep voltage levels are
programmable and are explained in the “STV, DSV and
DRSV” section of this document.
Deep Sleep Enable-DSEN# and Deeper Sleep
Enable - DRSEN
Table 2 shows logic states controlling modes of operation.
Figure 6 and Figure 7 shows the timing for transitions
FIGURE 5.
STP_CPU#
(DSEN#)
V CC_CORE
VID[0..5]
VID[0..5]
V CC_CORE
PGOOD
VID[0..5]
STP_CPU#
(DSEN#)
DPRSLPVR
(DRSEN)
V CC_CORE
FIGURE 6.
PLOT SHOWING TIMING OF VID CODE CHANGES AND CORE VOLTAGE SLEWING AS WELL AS PGOOD MASKING
CORE VOLTAGE SLEWING TO 98.8% OF PROGRAMMED VID VOLTAGE FOR A LOGIC LEVEL LOW ON DSEN
HIGH
V Deep Sleep
Current Voltage Level
Current VID Code
V Deeper Sleep
11
FIGURE 7.
VID Command Voltage
< 600ns
V Deep Sleep
VCORE RESPONSE FOR DEEPER SLEEP COMMAND
Deeper Sleep Mode
VID Code remains the same
Short DPRSLP causes
VID Code remains the same
V CC-CORE
ISL6217
New VID Code
entering and exiting Deep Sleep Mode and Deeper Sleep
Mode. This is controlled by the system signals STPCPU#
and DPRSLPVR. ISL6217 pins DSEN#, (Deep Sleep
Enable #) and DRSEN, (Deeper Sleep Enable), are
connected to these 2 signals, respectively.
When DSEN# is logic high, and DRSEN is logic low, the
controller will operate in Active Mode and regulate the
output voltage to the VID commanded DAC voltage, minus
the voltage “Droop” as determined by the load current.
Voltage “Droop” is the reduction of output voltage
proportional to output current.
When a logic low is detected at the DSEN# and DRSEN
pins, the controller will regulate the output voltage to the
voltage seen on the DSV pin minus “Droop”. If the PWRCH
pin is connected to the DSEN# pin then the controller will
also switch to single channel operation.
to ramp up
New Voltage Level
<30us