ISL6261CRZ-T Intersil, ISL6261CRZ-T Datasheet - Page 16

• Manufacturer Part Number: ISL6261CRZ-T
• Description: IC CTRLR BUCK 1PHASE 40-MLFP
• Manufacturer: Intersil

Specifications of ISL6261CRZ-T

• Applications: Converter, Intel IMVP-6
• Voltage - Input: 5 ~ 21 V
• Number Of Outputs: 1
• Voltage - Output: 0.3 ~ 1.5 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN, 40-VFQFPN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

given in the IMVP-6
the SOFT capacitor, C
If SLEWRATE is 10mV/μs, and I
is calculated as
Choosing 0.015μF will guarantee 10mV/μs SLEWRATE at
minimum I
startup slew rate as well. One should expect the output
voltage to slew to the Boot value of 1.2V at a rate given by
the following equation:
Selecting Rbias
To properly bias the ISL6261, a reference current needs to be
derived by connecting a 147k, 1% tolerance resistor from the
RBIAS pin to ground. This provides a very accurate 10μA
current source from which OCSET reference current is derived.
Caution should used in layout: This resistor should be
placed in the close proximity of the RBIAS pin and be
connected to good quality signal ground. Do not connect any
other components to this pin, as they will negatively impact
the performance. Capacitance on this pin may create
instabilities and should be avoided.
C
C
dV
SOFT
SOFT
dt
FIGURE 6. SIMPLIFIED VOLTAGE DROOP CIRCUIT WITH CPU-DIE VOLTAGE SENSING AND INDUCTOR DCR CURRENT SENSING
soft
=
VDIFF
=
=
C
OC
200
SLEWRATE
Internal to
GV
I
SOFT
ISL6261
ss
value. This choice of C
μA
I
GV
=
0
(
10
.
41
015
®
mV
specification, determines the choice of
μA
SOFT
1
1
μF
μs
, through the following equation:
=
16
)
2
=
.
8
GV
10uA
mV
20
DROOP
is typically 200μA, C
nF
SOFT
μs
controls the
DROOP
OCSET
VSUM
VSEN
DFB
RTN
VO
1000pF
1000pF
330pF
(EQ. 2)
(EQ. 3)
(EQ. 4)
SOFT
R
ocset
ISL6261
0~10
Startup Operation - CLK_EN# and PGOOD
The ISL6261 provides a 3.3V logic output pin for CLK_EN#.
The system 3.3V voltage source connects to the 3V3 pin,
which powers internal circuitry that is solely devoted to the
CLK_EN# function. The output is a CMOS signal with 4mA
sourcing and sinking capability. CMOS logic eliminates the
need for an external pull-up resistor on this pin, eliminating
the loss on the pull-up resistor caused by CLK_EN# being
low in normal operation. This prolongs battery run time. The
3.3V supply should be decoupled to digital ground, not to
analog ground, for noise immunity.
At startup, CLK_EN# remains high until 20μs after PGD_IN
going high, and Vcc-core is regulated at the Boot voltage.
The ISL6261 triggers an internal timer for the
IMVP6_PWRGD signal (PGOOD pin). This timer allows
PGOOD to go high approximately 7ms after CLK_EN# goes
low.
Static Mode of Operation - Processor Die Sensing
Remote sensing enables the ISL6261 to regulate the core
voltage at a remote sensing point, which compensates for
various resistive voltage drops in the power delivery path.
The VSEN and RTN pins of the ISL6261 are connected to
Kelvin sense leads at the die of the processor through the
processor socket. (The signal names are Vcc_sense and
Vss_sense respectively). Processor die sensing allows the
voltage regulator to tightly control the processor voltage at
the die, free of the inconsistencies and the voltage drops due
I
phase
VCC-SENSE
VSS-SENSE
R
s
L
Socket Kelvin
To Processor
Conections
DCR
V
o
September 27, 2006
ESR
C
o
FN9251.1