ADP3156JR-2.5 Analog Devices Inc, ADP3156JR-2.5 Datasheet - Page 7

• Manufacturer Part Number: ADP3156JR-2.5
• Description: IC REG BUCK DUAL SW 2.5V 16-SOIC
• Manufacturer: Analog Devices Inc

Specifications of ADP3156JR-2.5

• Rohs Status: RoHS non-compliant
• Applications: Controller, Intel Pentium® III
• Voltage - Input: 3V, 5V
• Number Of Outputs: 2
• Voltage - Output: 2.5V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)

During the standby operating state, the 12 V, 5 V and 3.3 V
power supply outputs are disabled, and only a low power 5 V
rail (5VSB) is available. The circuits that must remain active in
standby must be able to run from 5VSB. To accomplish this,
power routing is required to allow switching between normal
and standby supplies. Lack of a 12 V rail in standby makes control
of linear outputs difficult, and with up to 8 A demand from the
1.5 V and 1.8 V rails, an all-linear solution is inefficient.
Figure 13 shows a typical ACP-compliant Pentium III / chipset
power management system using the ADP3155 and ADP3156.
The ADP3155 provides VID switched output and two linear
regulators for standby operation. A charge-pump-doubled 5VSB is
ORed into the supply rail to supply the linear regulators during
standby operation. The VID output collapses when the main
5 V rail collapses, but the N-channel MOSFET linear regu-
lators can continue to supply current from the ~9 V supply.
The ADP3156 provides 1.8 V via its main switching regulator,
and allows efficient linear regulation of 1.5 V rail by using the
1.8 V output as its source.
The design parameters for an ACPI-compliant Pentium III
peripheral system depend on what peripherals are used
(e.g., AGP) and what their specifications are. The following is
an example where the higher of two low system voltages (1.8 V
and 1.5 V) is created directly with the main buck converter, and
also used to supply power for the lower output voltage using the
ADP3156’s linear regulator controller.
Input voltage (power source): V
Auxiliary voltage: V
Output voltages and tolerances: V
5%
Maximum output currents: I
REV. 0
(OR NLX)
SUPPLY
POWER
ATX_SHUTDOWN
ATX
ATX_PGOOD
5V_ALWAYS
VDDQ FOR AGP
TYPEDET# FOR
GND
3.3V
AGP SELECT
12V
1.5V OR 3.3V
5V
MEM, ETC
SB CORE,
1.8V FOR
FOR GTL
1.5V VTT
CC
12V
5V
3.3V
5V_PM
ATX_POWERGOOD
ATX_SHUTDOWN
= 12 V
1MAX
OUT
OUT
VDDQ
SELECT
IN
OUTPUT
SUPPLY
Figure 13. ACPI-Compliant Pentium III System Block Diagram
DUAL
POWER ROUTING
1
= 3 A, I
= 5 V
= 1.8 V
SWITCHER
POWER MANAGEMENT
LINEAR
ATX_POWER GOOD
STATE COMMAND
2MAX
3.3V_IN
1.5V_IN
CTRLS
CTRLS
5%, V
= 4 A
IN
IN
5V_PM
CTRLS
MAIN_
12V
V
2
CC
= 1.5 V
ADP3156
5V
3.3V
ATXPG
PMSC
5V_PM
CTRLS
LIN_
–7–
MANAGEMENT
FUNCTIONS
Slew rate of load current change: di
The absence of an inductor on the 1.5 V linear regulated output
allows the output current to respond quickly and the linear
regulator MOSFET’s resistance to be modulated quickly. This,
and some small bypassing capacitors, essentially insulates the
1.5 V output from transient activity on the 1.8 V output. How-
ever, this same fast response characteristic means that any 1.5 V
transient activity will be passed straight through the linear regu-
lator to the 1.8 V output. This means that the 1.8 V output filter
capacitor selection must consider both 1.8 V and 1.5 V load
transients.
In this design example, worst case consideration requires that
the 1.8 V output be designed for transient current loading of
I
tor design will have a current slew rate of <1 A/ s due to the
inductor, nearly the entire 7 A transient current must be ab-
sorbed by the output capacitors.
C
The ADP3156 uses a constant-off-time architecture with t
determined by an external timing capacitor C
high side N-channel MOSFET switch turns on, the voltage
across C
C
2.3 V, a new on-time cycle is initiated. The value of the off-time
is calculated using the continuous-mode operating frequency.
Assuming a nominal operating frequency of f
an output voltage of 1.8 V, the corresponding off-time is:
The timing capacitor can be calculated from the equation:
LIN#2_
CTRLS
1MAX
POWER
T
T
Selection for Operating Frequency
is discharged by a constant current of 65 A. Once C
5V_PM
5V_PM
ADP3155
+ I
5V
T
2MAX
is reset to approximately 3.3 V. During the off-time,
CTRLS
LIN#1_
V
CC
= 7 A. Also, because a practical switching regula-
t
OFF
C
12V
T
V
VID_4:0
CC
CTRLS
MAIN_
t
1
OFF
–
IN
CTRLS
CTRLS
CTRLS
IN
IN
V
V
1
IN
O
V
65
SWITCHER
LINEAR#1
LINEAR#2
VID
f
A
NOM
1
1
/dt = di
OUTPUT
SUPPLY
TRIPLE
208
OUT
OUT
OUT
3 2
2
.
pF
/dt >10 A/ s
NOM
T
ADP3156
. Each time the
s
CPU
V
3.3V_PM
FOR POWER
MANAGEMENT
2.5V_PM
FOR CMOS,
CLOCK, MEMORY
= 200 kHz at
CORE
@ VID
T
reaches
OFF