EL7585AILZ-T13 Intersil, EL7585AILZ-T13 Datasheet - Page 14

• Manufacturer Part Number: EL7585AILZ-T13
• Description: IC POWER SUPPLY TFT-LCD 20-QFN
• Manufacturer: Intersil

Specifications of EL7585AILZ-T13

• Applications: Converter, TFT, LCD
• Voltage - Input: 3 ~ 5 V
• Number Of Outputs: 4
• Voltage - Output: 5.5 ~ 20 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The following equation gives the boundary between
discontinuous and continuous boost operation. For
continuous operation (LX switching every clock cycle) we
require that:
I(A
where the duty cycle, D = (A
For example, with V
12V we find continuous operation of the boost converter can
be guaranteed for:
L = 10µH and I(A
L = 6.8µH and I(A
L = 3.3µH and I(A
Charge Pump Output Capacitors
Ceramic capacitors with low ESR are recommended. With
ceramic capacitors, the output ripple voltage is dominated by
the capacitance value. The capacitance value can be
chosen by the following equation:
C
where f
Start-Up Sequence
Figure 26 shows a detailed start-up sequence waveform. For
a successful power-up, there should be six peaks at V
When a fault is detected, the device will latch off until either
EN is toggled or the input supply is recycled.
When the input voltage (V
V
internal current source starts to charge C
threshold using a fast ramp followed by a slow ramp. If EN is
low at this point, the C
goes high.
The first four ramps on C
initialize the fault protection switch and to check whether
there is a fault condition on C
detected, the outputs and the input protection will turn off,
but V
ramping up and down.
During the second ramp, the device checks the status of
V
PG output goes low and enables the input protection PMOS
Q1. Q1 is a controlled FET used to prevent in-rush current into
V
on is controlled by C
off and disconnect the inductor from V
With the input protection FET on, NODE1 (See Typical
Application Diagram) will rise to ~V
enabled so V
diode. Hence, there is a step at V
REF
BOOST
OUT
LOGIC
VDD
REF
≥
and over temperature. At the peak of the second ramp,
_load) > D*(1-D)*V
OSC
------------------------------------------------------
2
turn on. At the same time, if EN is tied to V
before V
×
will stay on. If no fault is found, C
V
RIPPLE
is the switching frequency.
BOOST
I
OUT
VDD
BOOST
VDD
VDD
×
IN
o
rises to V
. When a fault is detected, M1 will turn
) > 61mA
f
) > 89mA
) > 184mA
OSC
DLY
= 5V, F
DLY
is enabled internally. Its rate of turn
IN
DD
ramp will be delayed until EN
/(2*L*F
VDD
14
) exceeds 2.5V, V
(two up, two down) are used to
DLY
OSC
IN
-V
BOOST
- V
or V
DIODE
IN
= 1.0MHz and A
OSC
IN
. Initially the boost is not
IN
REF
)/A
.
)
during this part of the
VDD
DLY
through the output
. If a fault is
CDLY
to an upper
REF
continues
VDD
DD
and
CDLY
, an
=
EL7585A
.
start-up sequence. If this step is not desirable, an external
PMOS FET can be used to delay the output until the boost is
enabled internally. The delayed output appears at A
For EL7585A, V
ramp. The soft-start ramp depends on the value of the C
capacitor. For C
V
peak, the open drain o/p DELB goes low to turn on the
external PMOS Q4 to generate a delayed V
V
PG, V
Fault Protection
During the startup sequence, prior to BOOST soft-start,
V
device temperature is checked. If either of these are not
within the expected range, the part is disabled until the
power is recycled or EN is toggled.
If C
while if C
occur and the sequence will not complete.
Once the start-up sequence is completed, the chip
continuously monitors C
FBB and PG and checks for faults. During this time, the
voltage on the C
fault is detected, or the EN pin is pulled low.
A fault on C
chip immediately. If a fault on any other output is detected,
C
the upper fault threshold (typically 2.4V), at which point the
chip is disabled until the power is recycled or EN is toggled.
If the fault condition is removed prior to the end of the ramp,
the voltage on the C
Typical fault thresholds for FBP, FBL, FBN and FBB are
included in the tables. PG and DELB fault thresholds are
typically 0.6V.
C
voltage within its normal range. If C
boost regulator will attempt to regulate to 0V. If C
shorted H, the regulator switches to P mode.
If any of the regulated outputs (V
V
circuitry will switch off until the output returns to its expected
value.
If V
prevent damage to the chip. While in current limit, the part
acts like a current source and the regulated output will drop.
If the output drops below the fault threshold, a ramp will be
initiated on C
the chip will be disabled on completion of the ramp.
OFF
ON
REF
LOGIC
DELAY
INT
BOOST
DELAY
is enabled at the beginning of the sixth ramp. A
has an internal current-limited clamp to keep the
OFF
turns on at the start of the fourth peak. At the fifth
is checked to be within ±20% of its final value and the
) are driven above their target levels the drive
will ramp up linearly with a 5µA (typical) current to
DELAY
, DELB and V
is shorted low, then the sequence will not start,
is excessively loaded, the current limit will
DELAY
DELAY
BOOST
DLY
DLY
is shorted H, the first down ramp will not
, V
DLY
and, provided that the fault is sustained,
of 220nF, the soft-start time is ~2ms.
capacitor remains at 1.15V until either a
REF
ON
soft-start at the beginning of the third
DLY
capacitor returns to 1.15V.
or temperature will shut down the
are checked at end of this ramp.
, DELB, FBP, FBL, FBN, V
BOOST
INT
is shorted low, the
, V
ON
BOOST
, V
OFF
INT
VDD
March 9, 2006
output.
VDD
is
or
FN7523.3
REF
.
DLY
,
,