MAX15021ATI+ Maxim Integrated Products, MAX15021ATI+ Datasheet - Page 18

• Manufacturer Part Number: MAX15021ATI+
• Description: IC REG SYNC DUAL 28-TQFN-EP
• Manufacturer: Maxim Integrated Products
• Type: Step-Down (Buck)r

Specifications of MAX15021ATI+

• Internal Switch(s): Both
• Synchronous Rectifier: Yes
• Number Of Outputs: 2
• Voltage - Output: 0.6 ~ 5.5 V
• Current - Output: 2A, 4A
• Frequency - Switching: 500kHz ~ 4MHz
• Voltage - Input: 2.5 ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 28-TQFN Exposed Pad
• Power - Output: 2.76W
• Topology: Buck
• Output Voltage: 0.6 V to 5.5 V
• Output Current: 2 A, 4 A
• Input Voltage: 2.5 V to 5.5 V
• Duty Cycle (max): 100 %
• Switching Frequency: 500 KHz to 4 MHz
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V to 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Solving for R
where V
L is the value of the regulator inductor, ESR is the
series resistance of the output capacitor, and V
the desired output voltage.
1) C
2) C
3) Calculate R
where V
of the regulator.
As indicated above, the position of the output capaci-
tor’s inherent ESR zero is critical in designing an appro-
priate compensation network. When low-ESR ceramic
output capacitors (MLCCs) are used, the ESR zero fre-
quency (f
crossover frequency (f
pensation network is recommended (see Figure 6a).
As shown in Figure 6b, the Type III compensation net-
work introduces two zeros and three poles into the con-
trol loop. The error amplifier has a low-frequency pole
at the origin, two zeros, and two higher frequency poles
at the following frequencies:
Two midband zeros (f
pensate for the pair of complex poles introduced by the
LC filter.
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Tracking/Sequencing Capability
18
zero, f
quency pole, f
______________________________________________________________________________________
F
CF
is determined from the compensator’s leading
R [k ]
FB
FB
is determined from the compensator’s high-fre-
1
Z1
ESR
R [k ] R [k ]
= 0.6V (typ) and V
is the 0.6V (typ) FB_ input-voltage set-point,
2
C
, and R
Ω
1
C [ F]
Type III: Compensation when f
CF
) is usually much higher than the desired
:
F
Ω
2
=
[µ
µ
using the following equation:
f
2
=
Z2
P1
F]
R [k ] 4 ESR[m ] V
π
F
f
F
Z1
, and R
×
=
=
1
=
as follows:
f
2
CO
Z1
2
2
=
CO
Ω
π
π
Ω
π
2
×
and f
[kHz] L[ H] V
×
×
× ×
). In this case, a type III com-
π
R [k ] f [kHz]
×
R [k ] f [kHz]
C
F
×
F
V
F
I
as follows:
R
OUT_
×
OUT_
1
1
Z2
F
×
Ω
(R
Ω
1
×
1
) are designed to com-
1
V
×
C
×
µ
FB
[V] V
+
F
is the output voltage
Z1
P1
R )
Ω
I
−
[V]
×
×
FB
OUT_
FB
[V]
[V]
CO
[V]
OUT_
< f
ESR
is
f
nulling DC output voltage errors.
Depending on the location of the ESR zero (f
can be used to cancel it, or to provide additional atten-
uation of the high-frequency output ripple.
f
Since C
Figure 6b. Type III Compensation Network Response
Figure 6a. Type III Compensation Network
P1
P3
GAIN
(dB)
attenuates the high-frequency output ripple.
C
introduces a pole at zero frequency (integrator) for
R
I
f
I
P3
(AT ORIGIN)
1ST POLE
CF
=
1ST ASYMPTOTE
2
<< C
R
R
(ωR
π
1
2
V
OUT_
×
1
C
R
F
)
2ND ASYMPTOTE
-1
1ST ZERO
F
F
(R
f
P1
f
P3
F
×
then:
C
V
1
( )
F
= at the origin (0Hz)
(
)
FB_
REF
f
C C
R
R
-1
P2
=
F
1
2ND ZERO
F
(R
2
1
1
C
=
π
I
)
-1
2
CF
×
2ND POLE
π
3RD ASYMPTOTE
(ωR
(R
R
C
R
)
×
F
I
CF
C
1
F
F
=
I
4TH ASYMPTOTE
R
)
C
1
-1
×
I
I
)
2
-1
C
×
π
( )
C
CF
R
×
R
C
F
I
I
R
F
F
3RD POLE
(R
×
F
C
1
C
C
CF
F
F
)
-1
×
+
5TH ASYMPTOTE
(ωR
C
C
ω (rad/sec)
ESR
CF
CF
I
COMP_
C
CF
)
-1
), f
P2