LTC1871EMS#TRPBF Linear Technology, LTC1871EMS#TRPBF Datasheet - Page 22

• Manufacturer Part Number: LTC1871EMS#TRPBF
• Description: IC CONTRLR CURRENT MODE 10-MSOP
• Manufacturer: Linear Technology
• Type: Step-Up (Boost), Flyback, Sepicr

Specifications of LTC1871EMS#TRPBF

• Internal Switch(s): No
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Voltage - Output: 1.23 ~ 72 V
• Current - Output: 50mA
• Frequency - Switching: 50kHz ~ 1MHz
• Voltage - Input: 2.5 ~ 36 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Number Of Pwm Outputs: 1
• On/off Pin: No
• Adjustable Output: No
• Topology: Boost/Buck/Flyback
• Switching Freq: 50 TO 1000kHz
• Duty Cycle: 97%
• Operating Supply Voltage (max): 36V
• Synchronous Pin: Yes
• Rise Time: 17ns
• Fall Time: 8ns
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 10
• Package Type: MSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -
• Lead Free Status / Rohs Status: Compliant

LTC1871
APPLICATIONS INFORMATION
8. The choice of an input capacitor for a boost converter
PC Board Layout Checklist
1. In order to minimize switching noise and improve output
2. Beware of ground loops in multiple layer PC boards.
3. Place the C
4. The high di/dt loop from the bottom terminal of the
22
(JMK325BJ226MM) are added for HF noise reduction.
Check the output ripple with a single oscilloscope
probe connected directly across the output capacitor
terminals, where the HF switching currents fl ow.
depends on the impedance of the source supply and
the amount of input ripple the converter will safely tol-
erate. For this particular design and lab setup a 100μF
Sanyo Poscap (6TPC 100M), in parallel with two 22μF
Taiyo Yuden ceramic capacitors (JMK325BJ226MM)
is required (the input and return lead lengths are kept
to a few inches, but the peak input current is close to
20A!). As with the output node, check the input ripple
with a single oscilloscope probe connected across the
input capacitor terminals.
load regulation, the GND pin of the LTC1871 should be
connected directly to 1) the negative terminal of the
INTV
of the output decoupling capacitors, 3) the source of
the power MOSFET or the bottom terminal of the sense
resistor, 4) the negative terminal of the input capacitor
and 5) at least one via to the ground plane immediately
adjacent to Pin 6. The ground trace on the top layer of
the PC board should be as wide and short as possible
to minimize series resistance and inductance.
Try to maintain one central ground node on the board
and use the input capacitor to avoid excess input ripple
for high output current power supplies. If the ground
plane is to be used for high DC currents, choose a path
away from the small-signal components.
INTV
tor carries high di/dt MOSFET gate drive currents. A
low ESR and ESL 4.7μF ceramic capacitor works well
here.
output capacitor, through the power MOSFET, through
the boost diode and back through the output capacitors
CC
CC
decoupling capacitor, 2) the negative terminal
and GND pins on the IC package. This capaci-
VCC
capacitor immediately adjacent to the
5. Check the stress on the power MOSFET by measuring
6. Place the small-signal components away from high
7. If a sense resistor is used in the source of the power
8. For optimum load regulation and true remote sensing,
9. For applications with multiple switching power convert-
should be kept as tight as possible to reduce inductive
ringing. Excess inductance can cause increased stress
on the power MOSFET and increase HF noise on the
output. If low ESR ceramic capacitors are used on the
output to reduce output noise, place these capacitors
close to the boost diode in order to keep the series
inductance to a minimum.
its drain-to-source voltage directly across the device
terminals (reference the ground of a single scope probe
directly to the source pad on the PC board). Beware
of inductive ringing which can exceed the maximum
specifi ed voltage rating of the MOSFET. If this ringing
cannot be avoided and exceeds the maximum rating
of the device, either choose a higher voltage device
or specify an avalanche-rated power MOSFET. Not all
MOSFETs are created equal (some are more equal than
others).
frequency switching nodes. In the layout shown in
Figure 14, all of the small-signal components have
been placed on one side of the IC and all of the power
components have been placed on the other. This also
allows the use of a pseudo-Kelvin connection for the
signal ground, where high di/dt gate driver currents
fl ow out of the IC ground pin in one direction (to the
bottom plate of the INTV
small-signal currents fl ow in the other direction.
MOSFET, minimize the capacitance between the SENSE
pin trace and any high frequency switching nodes. The
LTC1871 contains an internal leading edge blanking time
of approximately 180ns, which should be adequate for
most applications.
the top of the output resistor divider should connect
independently to the top of the output capacitor (Kelvin
connection), staying away from any high dV/dt traces.
Place the divider resistors near the LTC1871 in order
to keep the high impedance FB node short.
ers connected to the same input supply, make sure
CC
decoupling capacitor) and
1871fe