LT1507CS8-3.3 Linear Technology, LT1507CS8-3.3 Datasheet - Page 17

• Manufacturer Part Number: LT1507CS8-3.3
• Description: IC SW REG BUCK MODE 3.3V 8-SOIC
• Manufacturer: Linear Technology
• Type: Step-Down (Buck)r

Specifications of LT1507CS8-3.3

• Internal Switch(s): Yes
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Voltage - Output: 3.3V
• Current - Output: 1.5A
• Frequency - Switching: 500kHz
• Voltage - Input: 4 ~ 15 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

APPLICATIONS
works by prematurely tripping the oscillator before it
reaches its normal peak value. For instance, if the oscilla-
tor is synchronized at twice its nominal frequency, oscil-
lator amplitude will drop by half. A ramp which previously
started at the 40% point now starts at the 80% point! This
effectively blocks slope compensation and the regulator
may respond with fluctuating pulse widths, a “phase
oscillation” if you will. The regulator output stays in
regulation but subharmonic frequencies are generated at
the switch node.
The solution to this problem is to generate an external
ramp that replaces the missing internal ramp. As it turns
out, this is not difficult if the sync signal can be arranged
to have a fairly low duty cycle (< 35%). The ramp is created
by AC coupling a resistor from the sync signal to the
compensation capacitor as shown in Figure 7. This gener-
ates a negative ramp on the V
that emulates the missing internally generated ramp.
Amplitude of the ramp should be about 100mV to 200mV
peak-to-peak. The formulas for calculating the values of
R
unimportant as long as it exceeds the value given. The
formula assures that the impedance of C
compared to R
V
DC
V
f = Sync frequency
Theoretical minimum amplitude for the ramp, assuming
no internal ramp, is:
g
(1.8A/V for the LT1507).
mP
SYNC
P-P
S
R
C
S
V
and C
P-P
S
S
= Duty cycle of incoming sync signal
= Transconductance from V
= Desired amplitude of ramp
= Peak-to-peak value of sync signal
2
V
S
SYNC
2
are shown below. Note that the C
20
f R
V
OUT
V
S
P-P
2
.
DC
S
f L g
S
C
U
V
C
IN
1
f
mP
INFORMATION
1
DC
U
DC
S
C
pin during switch ON time
S
C
pin to switch current
W
S
will be small
S
U
value is
For V
To avoid small values of R
should be made as small as possible. 2000pF will work in
most situations. If we increase V
cushion, R
THERMAL CALCULATIONS
Power dissipation in the LT1507 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit
current and input quiescent current. The formulas below
show how to calculate each of these losses. These formu-
las assume continuous mode operation, so they should
not be used for calculating efficiency at light load currents.
Switch loss:
Boost current loss:
Quiescent current loss:
R
16ns = Equivalent switch current/voltage overlap time
f = Switching frequency
SW
R
C
P
P
P
V
SW
BOOST
Q
P-P
S
IN
= Switch resistance ( 0.4 )
= 4.7, V
2 1 10
V
0 09 2 10
IN
2 1 10
S
.
R
( .
SW OUT
will be:
0 003
( )( . )( . )
6 6 4 7 1 0 25
V
OUT
5 0 25 0 75
OUT
(
V
20
I
6
IN
= 3.3V, f = 1MHz, L = 5 H and DC
6
V
)
2
IN
5200
9
) (
2
V
0 008
5 10
OUT
.
V
S
, the compensation capacitor (C
OUT
1 10
( .
0 005
6
612
)
6
I
OUT
75
16
1 8
pF
PP
)
ns I
5 2
.
to 90mV for a little
(
71
OUT
k
mV
)(
V
LT1507
IN
)( )
S
f
17
= 25%:
C
)